EP2SGX60CF780C7 vs EP2SGX60CF780C5 对比

详细并排对比 EP2SGX60CF780C7 出自 Altera 和 EP2SGX60CF780C5 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2SGX60CF780C7 EP2SGX60CF780C5
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $215.00 $162.00
Family Stratix II GX —
Logic Elements 60,440 60,440
Adaptive Logic Modules (ALMs) [DATA_NEEDED: ALM count] —
Embedded Memory Bits 2,544,192 bits 2,544,192 bits
DSP Blocks 24 (18x18 multipliers) Yes (TriMatrix embedded multiplier blocks)
Maximum User I/O 364 —
Transceiver Channels 12 —
Transceiver Data Rate 600 Mbps to 6.375 Gbps —
Core Voltage 1.2 V 1.2 V
Process Node 90 nm —
Speed Grade C7 C5 (commercial)
封装 780-ball FCBGA 780-ball FC-FBGA (29x29 mm, 1 mm pitch)
Ball Pitch 1.0 mm —
工作温度 0C to +85C (commercial) —
Configuration Scheme Enhanced Configuration (EPC) —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant
Device Family — Stratix II GX
Logic Array Blocks (LABs) — 3,022
Maximum User I/Os — 364
引脚数 — 780
Maximum Internal Frequency — 717 MHz
Propagation Delay — [DATA_NEEDED: propagation delay in ns]
Process Technology — 90 nm CMOS
Temperature Grade — Commercial (0C to +85C)
Transceivers — Up to 20 multi-gigabit transceivers
PLLs — 4 enhanced PLLs + 8 fast PLLs
Configuration Schemes — Passive Serial, Fast Passive Parallel, JTAG
Memory Interfaces — DDR/DDR2 SDRAM controllers with source-synchronous PHY
安装类型 — Surface Mount
Lead-Free — Yes
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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