EP3C16U484C8 vs EP3C16F484C7N 对比

详细并排对比 EP3C16U484C8 出自 Altera 和 EP3C16F484C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3C16U484C8 EP3C16F484C7N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
Device Type Field Programmable Gate Array (FPGA) —
FPGA Family Cyclone III —
Logic Cells 15,408 —
Logic Blocks 516,096 —
I/O Pins 346 —
封装 484-FBGA 484-ball FBGA
Package Type Other, LEAD FREE, MS-034 —
安装类型 Surface Mount —
工作温度 -40°C to +125°C 0C to +85C (commercial)
Core Supply Voltage [DATA_NEEDED: core supply voltage] —
I/O Supply Voltage [DATA_NEEDED: I/O supply voltage range] —
Memory Blocks [DATA_NEEDED: embedded memory block count] —
PLLs [DATA_NEEDED: PLL count] 4
最大时钟频率 [DATA_NEEDED: maximum clock frequency] —
Configuration Interface [DATA_NEEDED: supported configuration interfaces] —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant
REACH Status [DATA_NEEDED: REACH status] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification status] —
Lead-Free Status LEAD FREE —
Device Family — Cyclone III
Logic Elements — 15,408
Embedded Memory — 504 Kbits (M9K blocks)
Embedded Multipliers — 56 (18x18)
User I/O Pins — 346
Process Technology — 65 nm TSMC low-power
Core Voltage — 1.2 V (1.15 V to 1.25 V)
Speed Grade — -7
Maximum Internal Frequency — 437.5 MHz
I/O Standards Supported — LVDS, LVCMOS, LVTTL, SSTL, HSTL
Configuration Method — JTAG (IEEE 1149.1), EPCS serial flash, Active Serial

数据手册与资源

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