EP3SE50F484I4LN vs EP3SE50F484I3N 对比

详细并排对比 EP3SE50F484I4LN 出自 Intel 和 EP3SE50F484I3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SE50F484I4LN EP3SE50F484I3N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $895.00 $841.66
Family Stratix III E Stratix III E
Logic Elements (LE) 47,500 —
Logic Array Blocks (LABs) 1,900 —
Embedded Memory 5.76 Mbit (estimated from 47.5K LE family) —
User I/O Count 296 —
Process Node 65 nm —
Core Voltage (VCCINT) 0.9 V —
Auxiliary Voltage (VCCAUX) 1.1 V —
I/O Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V (bank-dependent) —
封装 484-ball FBGA (FineLine BGA) 484-pin FC-FBGA (flip-chip BGA)
Pin/Pitch 484 balls, 1.0 mm pitch —
工作温度 -40C to +100C (industrial I4 grade) -40C to +100C (industrial)
Configuration SRAM-based (external flash/EPCS required) —
RoHS 状态 Compliant (LN suffix indicates lead-free) —
Lead-Free Yes (LF / N suffix indicates lead-free) —
Transceivers 0 (F484 package does not include transceiver banks) —
PLL Count Up to 12 (estimated for Stratix III E family) —
DSP Blocks (18x18 Multipliers) [DATA_NEEDED: DSP block count] —
Design Tool Quartus II (legacy, support via Altera/Intel subscription) —
Logic Elements — 47,500
Number of LABs — 1,900
Total Memory Bits — 5,760,000
Maximum User I/O — 296
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Core Voltage VCC — 0.9 V
Auxiliary Voltage VCCAUX — 1.1 V
Process Technology — 65 nm
Maximum Internal Frequency — 500 MHz
Speed Grade — I3 (industrial, bin 3)
安装类型 — Surface Mount (BGA)
Lead-Free / RoHS — Yes (N suffix)
Configuration Method — Active serial (AS), passive serial (PS), JTAG, fast passive parallel (FPP)
DSP Blocks — [DATA_NEEDED: number of DSP blocks]
Embedded Multipliers (18x18) — [DATA_NEEDED: number of 18x18 multipliers]
Transceiver Count — [DATA_NEEDED: number of embedded transceivers]

数据手册与资源

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