EP3SE50F484I4LN vs EP3SE50F484I3N 비교
다음의 상세 나란히 비교: EP3SE50F484I4LN 제조: Intel 및 EP3SE50F484I3N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP3SE50F484I4LN | EP3SE50F484I3N |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $895.00 | $841.66 |
| Family | Stratix III E | Stratix III E |
| Logic Elements (LE) | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | — |
| Embedded Memory | 5.76 Mbit (estimated from 47.5K LE family) | — |
| User I/O Count | 296 | — |
| Process Node | 65 nm | — |
| Core Voltage (VCCINT) | 0.9 V | — |
| Auxiliary Voltage (VCCAUX) | 1.1 V | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V (bank-dependent) | — |
| 패키지 | 484-ball FBGA (FineLine BGA) | 484-pin FC-FBGA (flip-chip BGA) |
| Pin/Pitch | 484 balls, 1.0 mm pitch | — |
| 동작 온도 | -40C to +100C (industrial I4 grade) | -40C to +100C (industrial) |
| Configuration | SRAM-based (external flash/EPCS required) | — |
| RoHS 상태 | Compliant (LN suffix indicates lead-free) | — |
| Lead-Free | Yes (LF / N suffix indicates lead-free) | — |
| Transceivers | 0 (F484 package does not include transceiver banks) | — |
| PLL Count | Up to 12 (estimated for Stratix III E family) | — |
| DSP Blocks (18x18 Multipliers) | [DATA_NEEDED: DSP block count] | — |
| Design Tool | Quartus II (legacy, support via Altera/Intel subscription) | — |
| Logic Elements | — | 47,500 |
| Number of LABs | — | 1,900 |
| Total Memory Bits | — | 5,760,000 |
| Maximum User I/O | — | 296 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Voltage VCC | — | 0.9 V |
| Auxiliary Voltage VCCAUX | — | 1.1 V |
| Process Technology | — | 65 nm |
| Maximum Internal Frequency | — | 500 MHz |
| Speed Grade | — | I3 (industrial, bin 3) |
| 실장 유형 | — | Surface Mount (BGA) |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Configuration Method | — | Active serial (AS), passive serial (PS), JTAG, fast passive parallel (FPP) |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks] |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: number of 18x18 multipliers] |
| Transceiver Count | — | [DATA_NEEDED: number of embedded transceivers] |