EP3SE50F780C4N vs EP3SE50F780C4L 对比

详细并排对比 EP3SE50F780C4N 出自 Intel 和 EP3SE50F780C4L 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SE50F780C4N EP3SE50F780C4L
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $1,430.00 $1,320.00
Family Stratix III E Stratix III
Logic Elements (LE) 47,500 47,500
Embedded Memory Bits 5,760,000 —
Embedded Memory (M9K/M144K blocks) 488 (per family datasheet) —
Number of LABs 1900 —
Maximum User I/Os 488 —
DSP Blocks (18x18 multipliers) 432 304 (19x16)
PLLs 12 (per family datasheet) [DATA_NEEDED: PLL count]
Maximum Operating Frequency 717 MHz —
Transceiver Channels Up to 12 (per family, model-dependent) —
Transceiver Data Rate Up to 6.375 Gbps (per Stratix III E family) —
Process Node 40 nm 40 nm
封装 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch 780-ball FCBGA (Flip-Chip BGA)
安装类型 Surface Mount (BGA) —
电源电压 Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail) —
工作温度 0C to +85C (C4 commercial grade) [DATA_NEEDED: full industrial/commercial grade]
Configuration Modes JTAG, Passive Serial, Fast Passive Parallel —
RoHS 状态 Lead-free / RoHS compliant Compliant (lead-free)
MSL 等级 3 (per JEDEC J-STD-020, FBGA package) —
Hard Memory Controller DDR2/DDR3 SDRAM (per Stratix III E family) —
Series — Stratix III E
Embedded Memory — 5,760,000 bits
User I/Os — 488
Core Voltage — 1.1 V
Speed Grade — C4 (commercial, speed 4)
Lead-Free (L suffix) — Yes
Configuration Method — Passive Serial / Fast Passive Parallel / JTAG / Enhanced
Transceivers — [DATA_NEEDED: per Stratix III E variant]

数据手册与资源

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