EP3SL50F484I4 vs EP3SL50F484I4LG 对比

详细并排对比 EP3SL50F484I4 出自 Intel 和 EP3SL50F484I4LG 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL50F484I4 EP3SL50F484I4LG
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $558.00 $945.00
Device Family Stratix III L —
Logic Elements (LE) 47,500 —
Logic Array Blocks (LABs) 1,900 —
Embedded Memory Bits 2,184,192 bits —
Maximum User I/O 296 —
Process Technology 65 nm CMOS —
Internal Frequency 800 MHz (max, per digchip datasheet summary) —
Core Supply Voltage 1.1 V —
封装 484-ball FC-FBGA (FCBGA, 1.0 mm pitch) 484-Ball FCBGA (FBGA)
工作温度 -40C to +100C (industrial) -40C to +100C (Industrial)
Grade Suffix I4 = Industrial, speed grade 4 —
Configuration Modes JTAG, Passive Serial, FPP, PPA —
MultiTrack Interconnect Yes —
TriMatrix Embedded Memory MLAB, M9K, M144K blocks —
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 3 (168 hours) —
RoHS 状态 Compliant Compliant
Lead-Free Yes Yes
Family — Stratix III L
Series — EP3SL50
Logic Elements — 47,500
Embedded Memory — 2,184,192 bits (273 KB)
User I/Os — 296
Speed Grade — I4 (fast)
电源电压 — 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail)
Process Node — 40 nm
Total I/O Banks — [DATA_NEEDED: I/O bank count]
DSP Blocks — [DATA_NEEDED: DSP block count]
Transceivers — [DATA_NEEDED: transceiver channel count]
Configuration Memory — SRAM-based
Configuration Interface — JTAG / Passive Serial / Fast Passive Parallel

数据手册与资源

浏览全部产品 创建 BOM 获取报价