EP3SL50F484I4L vs EP3SL50F484I3N 对比
详细并排对比 EP3SL50F484I4L 出自 Intel 和 EP3SL50F484I3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP3SL50F484I4L | EP3SL50F484I3N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $658.26 | $552.30 |
| Series | Stratix III L (Low Power) | — |
| Family | Stratix III | Stratix III L |
| Logic Elements (LE) | 47,500 | — |
| Embedded Memory Bits | 2,184,192 bits (~273 KB) | — |
| User I/O Pins | 296 | — |
| 封装 | 484-ball FBGA (FCBGA) | 484-ball FBGA (FC-FBGA, 23x23 mm, 1.0 mm pitch) |
| Speed Grade | 4 | — |
| 工作温度 | 0 °C to 85 °C (commercial, per DigiKey listing) | — |
| 电源电压 | 0.9 V core (family-typical) | — |
| Process Technology | 65 nm low-power CMOS | 65 nm CMOS |
| 安装类型 | Surface Mount | Surface Mount (SMT) |
| Lead-Free / RoHS | Yes (RoHS compliant) | Lead Free / Compliant |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | — |
| Transceivers | Family supports up to 4 transceivers per family datasheet | — |
| DSP Blocks | Family supports up to 384 18x18 multipliers (family-level) | — |
| Logic Elements | — | 47,500 |
| Logic Array Blocks (LABs) | — | 1,900 |
| Embedded Memory | — | 2,184,192 bits (2.1 Mbit) |
| Embedded 18x18 Multipliers | — | 218 |
| Maximum User I/O | — | 296 |
| Core Voltage | — | 0.9 V / 1.1 V |
| Maximum Core Frequency | — | 500 MHz |
| 工作结温 | — | -40C to +100C (Industrial) |
| MSL 等级 | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Programming Tool | — | Quartus II (legacy) |