EP3SL50F780C4N vs EP3SE50F780C4N 对比

详细并排对比 EP3SL50F780C4N 出自 Intel 和 EP3SE50F780C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL50F780C4N EP3SE50F780C4N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $162.00 $1,430.00
Family Stratix III L Stratix III E
Series EP3SL50 —
Logic Elements (LEs) 47,500 —
Number of LABs / CLBs 1,900 —
Total RAM Bits 2,184,192 (273 KB) —
Number of User I/Os 488 —
Number of GPIO 488 —
封装 780-BBGA, FCBGA (FBGA-780) 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch
Process Technology 65 nm CMOS —
Speed Grade -4 —
工作温度 0C to +85C (commercial) 0C to +85C (C4 commercial grade)
Core Voltage Range 0.86 V to 1.15 V —
安装类型 Surface Mount Surface Mount (BGA)
Lead Free / RoHS Lead free, RoHS compliant per distributor listing —
Maximum Operating Frequency 717 MHz (per family) 717 MHz
DSP Blocks Hard DSP blocks (Stratix III family) —
Memory Interface Support DDR, DDR2, DDR3 (family feature) —
Logic Elements (LE) — 47,500
Embedded Memory Bits — 5,760,000
Embedded Memory (M9K/M144K blocks) — 488 (per family datasheet)
Number of LABs — 1900
Maximum User I/Os — 488
DSP Blocks (18x18 multipliers) — 432
PLLs — 12 (per family datasheet)
Transceiver Channels — Up to 12 (per family, model-dependent)
Transceiver Data Rate — Up to 6.375 Gbps (per Stratix III E family)
Process Node — 40 nm
电源电压 — Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail)
Configuration Modes — JTAG, Passive Serial, Fast Passive Parallel
RoHS 状态 — Lead-free / RoHS compliant
MSL 等级 — 3 (per JEDEC J-STD-020, FBGA package)
Hard Memory Controller — DDR2/DDR3 SDRAM (per Stratix III E family)

数据手册与资源

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