EP610DC-35 vs EP610DC-25 对比

详细并排对比 EP610DC-35 出自 Altera 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ 量产中

规格对比

参数 EP610DC-35 EP610DC-25
品牌 Altera Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $18.40 $9.95
Device Type CPLD - Classic EPLD —
Family Altera Classic EP610 Altera Classic EPLD
Macrocells 16 16
Usable Gates 300 —
Propagation Delay (tPD) 35 ns —
Maximum Frequency (fMAX) 28.6 MHz —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Process Technology CMOS —
Program/erase Method UV-erasable (windowed CERDIP) —
封装 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP, through-hole)
安装类型 Through-Hole (DIP) Through Hole
工作温度 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] 0 C to +70 C
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) —
RoHS 状态 [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] —
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Technology — CMOS EPROM (UV-erasable)
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

数据手册与资源

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