EP610DC-35 vs EP610DC-25 비교

다음의 상세 나란히 비교: EP610DC-35 제조: Altera 및 EP610DC-25 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ 활성

사양 비교

파라미터 EP610DC-35 EP610DC-25
브랜드 Altera Rochester Electronics
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND 활성
재고 상태 In Stock In Stock
단가 (USD) $18.40 $9.95
Device Type CPLD - Classic EPLD —
Family Altera Classic EP610 Altera Classic EPLD
Macrocells 16 16
Usable Gates 300 —
Propagation Delay (tPD) 35 ns —
Maximum Frequency (fMAX) 28.6 MHz —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Process Technology CMOS —
Program/erase Method UV-erasable (windowed CERDIP) —
패키지 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP, through-hole)
실장 유형 Through-Hole (DIP) Through Hole
동작 온도 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] 0 C to +70 C
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) —
RoHS 상태 [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] —
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Technology — CMOS EPROM (UV-erasable)
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

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