EP610DI-25 vs EP610DC-15 对比
详细并排对比 EP610DI-25 出自 Intel 和 EP610DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610DI-25 | EP610DC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $7.95 |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 15 ns (speed grade -15) |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | — |
| Dedicated Inputs | 4 | 20 |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| 引脚数量 | 24 | — |
| 安装类型 | Through-Hole (DIP) | Through-Hole |
| 工作温度 | Industrial (per "I" suffix) | 0C to 70C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| 封装 | — | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | — | JEDEC fuse map, UV erasure |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |