EP610DI-35 vs EP610DC-35 对比
详细并排对比 EP610DI-35 出自 Intel 和 EP610DC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete规格对比
| 参数 | EP610DI-35 | EP610DC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.85 | $18.40 |
| Family | Altera Classic EPLD | Altera Classic EP610 |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 20 (including 4 dedicated inputs) | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| 电源电压 | 5 V | — |
| Technology | CMOS, UV-erasable | — |
| 封装 | 24-pin CDIP (Ceramic DIP) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 安装类型 | Through-hole | Through-Hole (DIP) |
| 工作温度 | [DATA_NEEDED: industrial/commercial grade range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| RoHS 状态 | [DATA_NEEDED: not confirmed in supplied web data] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |