EP610IDC-15 vs EP610DM-35 对比
详细并排对比 EP610IDC-15 出自 Intel 和 EP610DM-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610IDC-15 | EP610DM-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $23.40 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| 工作温度 | 0C to +70C (commercial) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封装 | 24-pin CerDIP (ceramic DIP) | 24-pin CDIP (CERDIP) with UV window |
| 安装类型 | Through-hole | — |
| I/O Pins | 24 (per package; macrocell-programmable) | 24 dedicated I/O (input + bidirectional) |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status of CerDIP variant] | Non-compliant (contains lead, hermetic CERDIP) |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Manufacturer | — | Altera (Rochester Electronics authorized stock) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| Programmability | — | UV-erasable, reprogrammable |
| 工作温度范围 | — | -55°C to +125°C |
| MSL 等级 | — | [DATA_NEEDED: MSL rating] |