EP610ILC-10 vs EP610DC-25 对比

详细并排对比 EP610ILC-10 出自 Altera 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ 量产中

规格对比

参数 EP610ILC-10 EP610DC-25
品牌 Altera Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $7.20 $9.95
Device Family Classic EPLD —
Product Type UV-Erasable / OTP PLD EPLD (Erasable Programmable Logic Device)
Architecture PAL-type with macrocells —
Macrocells 16 16
Usable Gates 300 —
Product Terms 160 —
I/O Pins 16 —
Dedicated Inputs 4 —
电源电压 5 V (single supply) —
Pin-to-Pin Delay (tPD) 10 ns (grade -10) —
Counter Frequency (fCNT) 100 MHz —
Logic Family Compatibility TTL (5 V CMOS/TTL-compatible I/O) —
封装 PLCC-28 (plastic J-lead chip carrier) 24-pin CDIP (Ceramic DIP, through-hole)
安装类型 Surface Mount (PLCC socket or solder) Through Hole
工作温度 [DATA_NEEDED: operating temperature range] 0 C to +70 C
RoHS 状态 [DATA_NEEDED: RoHS compliance] —
Family — Altera Classic EPLD
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Pipelined Data Rate — Up to 100 MHz
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Technology — CMOS EPROM (UV-erasable)
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

数据手册与资源

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