EP610ILC-25 vs EP610JI-30 对比

详细并排对比 EP610ILC-25 出自 Altera 和 EP610JI-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP610ILC-25 EP610JI-30
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.85 $9.40
Family Classic EPLD (EP610 series) Altera Classic EPLD (EP610)
Device Type EEPLD (Electrically Erasable PLD) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 300 —
Macrocells 16 16
Product Terms 160 160
Maximum Operating Frequency (fMAX) 40 MHz —
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Nominal Supply Voltage 5 V —
Total Inputs 20 —
Dedicated Inputs 4 4
Bidirectional I/O Pins 16 —
工作温度范围 0 C to +70 C (commercial) —
封装 28-pin PLCC (J-lead) CQCC28 (windowed ceramic JLCC, J-bend)
安装类型 Surface Mount Surface Mount (JLCC)
Process Technology CMOS, electrically erasable CMOS
Programming Method In-system, electrically erasable —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Propagation Delay (tpd) — 30 ns (max)
Pipelined Data Rate — Up to 100 MHz
I/O Pins — 16
External Clocks — 2
电源电压 — 5 V (single supply)
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
工作温度 — -40C to +85C (industrial, per EP610 family suffix convention)
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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