EP610IPC-10 vs EP610DC-25 对比
详细并排对比 EP610IPC-10 出自 Altera 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 量产中规格对比
| 参数 | EP610IPC-10 | EP610DC-25 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.40 | $9.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | — |
| Product Terms | 160 total | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| Total Input Pins | 20 | — |
| 电源电压 | 5 V | — |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS EPROM (UV-erasable) |
| 封装 | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, through-hole) |
| 工作温度 | -40C to +85C (industrial) | 0 C to +70 C |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | JEDEC fuse-map / UV-erase |
| TTL Emulation | 100% TTL compatible | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| 安装类型 | — | Through Hole |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |