EP610LC-15 vs EP610DC-25 对比

详细并排对比 EP610LC-15 出自 Altera 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ 量产中

规格对比

参数 EP610LC-15 EP610DC-25
品牌 Altera Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $4.65 $9.95
Product Type Classic EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD (EP610) Altera Classic EPLD
Logic Elements / Macrocells 16 macrocells —
Equivalent Gates 300 gates 300
Propagation Delay (tpd) 15 ns —
Counter Frequency (fmax) 83.3 MHz —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (Vcc) 5 V (single supply) —
Process Technology CMOS —
封装 28-pin PLCC (J-lead, plastic OTP) 24-pin CDIP (Ceramic DIP, through-hole)
安装类型 Surface Mount Through Hole
引脚数 28 —
工作温度 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] 0 C to +70 C
Programming OTP (one-time programmable) —
RoHS 状态 unknown —
MSL 等级 [DATA_NEEDED: MSL rating] —
Macrocells — 16
Maximum Propagation Delay (tPD) — 25 ns
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Technology — CMOS EPROM (UV-erasable)
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

数据手册与资源

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