EP910DC-40 vs EP910DM883B 对比
详细并排对比 EP910DC-40 出自 Altera 和 EP910DM883B 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DC-40 | EP910DM883B |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.95 | $7.10 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND-OR-NOT, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 电源电压 | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| 封装 | DIP-40 (ceramic, through-hole) | CDIP-40 (Ceramic DIP, 40-pin) |
| 安装类型 | Through-Hole | Through-Hole (DIP) |
| RoHS 状态 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Manufacturer | — | Altera (now part of Intel) |
| Family | — | Classic EPLD - EP910 Series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Propagation Delay (tPD) | — | 40 ns (typical) |
| 最大时钟频率 | — | 25 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| 工作温度 | — | -55 °C to +125 °C (military) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |