EP910DI-30 vs EP910DC-35 对比

详细并排对比 EP910DI-30 出自 Rochester Electronics 和 EP910DC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910DI-30 EP910DC-35
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $17.60 $10.95
Product Type UV-Erasable Programmable Logic Device (EPLD) —
Family Classic EPLD (Altera EP910 series) Classic EPLD EP910
Macrocell Count 24 —
Propagation Delay (tpd) 30 ns 35 ns
Maximum Toggle Frequency (fmax) 62 MHz —
Supply Voltage (VCC) 5 V (single supply) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
封装 CDIP-40 (ceramic DIP, 40-pin with UV window) 40-pin CDIP (Ceramic DIP) with quartz window
安装类型 Through-Hole (DIP) —
Dedicated Inputs 10 12
Dedicated I/O Pins 12 (12 input + 12 output) —
Output Enable Pins 2 —
引脚数量 40 —
Programmable Logic Element JEDEC fuse map (3rd-party programmer) —
工作温度 -40C to +85C (industrial) 0 °C to +70 °C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Manufacturer (Original) Altera (now Intel PSG) —
Current Distributor / Authorized Aftermarket Rochester Electronics, LLC —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Macrocells — 24
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
最大时钟频率 — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Lifecycle — Obsolete / last-time-buy from authorized distributors

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