EP910DI-30 vs EP910DC-35 Comparação
Comparação detalhada lado a lado de EP910DI-30 por Rochester Electronics e EP910DC-35 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndComparação de especificações
| Parâmetro | EP910DI-30 | EP910DC-35 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $17,60 | $10,95 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD EP910 |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | 35 ns |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| Encapsulamento | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Tipo de montagem | Through-Hole (DIP) | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Contagem de pinos | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Temperatura de operação | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Frequência máxima de clock | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |