EP910DI-30 vs EP910DM-40 对比
详细并排对比 EP910DI-30 出自 Rochester Electronics 和 EP910DM-40 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd
规格对比
| 参数 | EP910DI-30 | EP910DM-40 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.60 | $21.00 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | UV Erasable Programmable Logic Device (EPLD) |
| Family | Classic EPLD (Altera EP910 series) | Altera Classic EP910 |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封装 | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 安装类型 | Through-Hole (DIP) | Through-Hole (DIP) |
| Dedicated Inputs | 10 | 36 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| 引脚数量 | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| 工作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | — | 24 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 电源电压 | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |