EP910DI-35 vs EP910DC-30 对比
详细并排对比 EP910DI-35 出自 Altera 和 EP910DC-30 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DI-35 | EP910DC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $35.20 | $15.60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 30 ns (max) |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 36 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| 封装 | CDIP-40 (Ceramic DIP with UV window) | DIP-40 (through-hole, 600 mil) |
| 安装类型 | Through-Hole | Through-Hole |
| 工作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | UV-Erasable / OTP |
| Erasure Method | UV light through quartz window | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | — |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| 电源电压 | — | 5 V |
| Process Technology | — | CMOS |