EP910IPC-15 vs EP910DC-30 对比
详细并排对比 EP910IPC-15 出自 Altera 和 EP910DC-30 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910IPC-15 | EP910DC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.95 | $15.60 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 30 ns (max) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作温度 | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| 封装 | PDIP-40 (Plastic DIP, 40-pin) | DIP-40 (through-hole, 600 mil) |
| 安装类型 | Through-Hole | Through-Hole |
| Process Technology | CMOS | CMOS |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | UV-Erasable / OTP |
| 引脚数量 | 40 | — |
| RoHS 状态 | [DATA_NEEDED: rohs status not confirmed in verified data] | — |
| Family | — | Classic EPLD (EP910 series) |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| 电源电压 | — | 5 V |