EP910LC-40H vs EP910ILC-50 对比
详细并排对比 EP910LC-40H 出自 Altera 和 EP910ILC-50 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910LC-40H | EP910ILC-50 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $10.85 |
| Family | Classic EPLD (EP910) | Altera Classic EPLD |
| Macro Cells | 24 | — |
| Usable Gates | 450 | 900 (typical) |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM, UV-erasable |
| 封装 | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | PLCC-44 (J-lead) |
| 安装类型 | Through-Hole (THT) | Surface Mount (socket-compatible) |
| 工作温度 | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | 0C to +70C (commercial) |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | — |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| RoHS 状态 | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | — | 24 |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| User I/O Pins | — | 24 |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |