EP910LC-40H vs EP910ILC-50 Comparison
Detailed side-by-side comparison of EP910LC-40H by Altera and EP910ILC-50 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-40H | EP910ILC-50 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $10.85 |
| Family | Classic EPLD (EP910) | Altera Classic EPLD |
| Macro Cells | 24 | β |
| Usable Gates | 450 | 900 (typical) |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | β |
| Propagation Delay (tPD) | 40 ns max | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | β |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM, UV-erasable |
| Package | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | PLCC-44 (J-lead) |
| Mounting Type | Through-Hole (THT) | Surface Mount (socket-compatible) |
| Operating Temperature | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | 0C to +70C (commercial) |
| Speed Grade | -40 (40 ns tPD) | β |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | β |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | β |
| RoHS Status | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | β | 24 |
| Maximum Frequency | β | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | β | 50 ns |
| User I/O Pins | β | 24 |
| Dedicated Input Pins | β | 12 |
| Programming Cycles | β | 100 (minimum) |
| Boundary Scan | β | IEEE 1149.1 JTAG (selected speed grades) |