EPC16QC100II vs EPC16QC100DM 对比

详细并排对比 EPC16QC100II 出自 Altera 和 EPC16QC100DM 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC100II EPC16QC100DM
品牌 Altera Intel
分类 Memory ICs Memory ICs
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $10.75 $15.85
存储器类型 FPGA Configuration PROM (Flash-based) Non-volatile Configuration PROM (NOR flash)
Memory Density 16 Mbit 16 Mbit (2 Mbyte)
Supported FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone —
Configuration Mode FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) —
Programmability In-System Programmable via IEEE 1149.1 (JTAG) —
Cascade Support Yes (multi-PROM cascading supported) —
Core Supply Voltage 3.3 V —
I/O Tolerance 5 V tolerant configuration pins —
封装 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (QFPA)
Package Dimensions 20 mm x 14 mm, 0.5 mm pitch —
Lead Finish Matte Tin (lead-free) —
工作温度 -40C to +85C (Industrial) —
MSL 等级 3 (per JEDEC J-STD-020) [DATA_NEEDED: MSL rating]
RoHS 状态 Compliant —
Configuration Pins DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE —
Compression Support Yes (reduces on-PROM footprint vs uncompressed bitstream) —
Configuration Interface — Serial (SPI-compatible, Altera FPP mode)
Core Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Voltage (VIO) — 2.5 V / 3.3 V selectable
Output Voltage (VPP) — 1.8 V / 2.5 V / 3.3 V selectable
Maximum DCLK Frequency — 40 MHz
Cascadable — Yes (multi-device daisy chain via nCASC)
In-System Programming — Yes (IEEE 1532 / JTAG)
Program/Erase Cycles — [DATA_NEEDED: program/erase cycle endurance]
Data Retention — [DATA_NEEDED: data retention years]
工作温度范围 — -40 C to +85 C (industrial)
Package Code — Q100 + DM suffix
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Compatible FPGA Families — Stratix, Cyclone, APEX, ACEX

数据手册与资源

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