EPC16UC80 vs EPC16QC100N 对比

详细并排对比 EPC16UC80 出自 Altera 和 EPC16QC100N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPC16UC80 EPC16UC80 - 16Mb Enhanced Config Device, 80-pin UBGA | Altera

EPC16UC80 - 16Mb Enhanced Config Device, 80-pin UBGA | Altera

EPC16UC80 ⚠ 最后一次采购

规格对比

参数 EPC16UC80 EPC16QC100N
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $11.75 $24.10
Memory Density 16 Mbit —
Device Family EPC4 / EPC8 / EPC16 Enhanced Configuration Device —
Configuration Memory Sections 8 (multi-boot capable) —
Supply Voltage (VCC) 3.0 V to 3.6 V (typical 3.3 V) 3.0 V to 3.6 V
Configuration Clock (DCLK) Up to 33 MHz (FPP mode) —
Configuration Modes FPP, PS, JTAG —
接口 Parallel data + DCLK + nSTATUS + nCONFIG + CONFIG_DONE —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Endurance 100,000 erase/program cycles (per datasheet) —
工作温度 -40 C to +85 C (industrial) 0 C to 70 C
封装 80-ball UBGA (Ultra FineLine BGA), 11x8 mm 100-pin PQFP (20 x 14 mm)
安装类型 Surface Mount Surface Mount
Supported Target FPGAs Stratix/II/III/GX, Cyclone/II/III, APEX 20K/II/IIE, Mercury —
Lead-Free / RoHS Compliant per Altera product page —
Multi-Device Daisy-Chain Yes —
存储容量 — 16 Mbit (16,777,216 bits)
Programmable Type — In System Programmable
Configuration Clock Frequency — 33 MHz max
On-Chip Decompression — Yes (supports compressed bitstreams)
Access Time — 90 ns typical
Flash Read Bandwidth — 160 Mbps (16-bit DQ at 10 MHz)
Configuration Interface — FPP / PS / AS via dedicated FPGA pins
JTAG (IEEE 1149.1) ISP — Supported
Lead Free — Yes (per datasheet)
Packaging — Tray
Supported FPGA Families — ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX

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