EPC16UC88NT vs EPC16UC88T 对比
详细并排对比 EPC16UC88NT 出自 Altera 和 EPC16UC88T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC16UC88NT | EPC16UC88T |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | Memory ICs | EEPROM |
| 生命周期状态 | 有效 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $9.95 |
| Device Type | Enhanced configuration device | — |
| Memory Capacity | 16 Mbit | — |
| Memory Technology | Flash memory | — |
| Primary Function | Configuration storage for SRAM-based FPGA devices | — |
| Programming Type | In-system programmable configuration PROM | — |
| 封装 | 88-UBGA | 88-ball UBGA, 11 mm x 8 mm |
| Package Dimensions | 11 mm by 8 mm | — |
| Configuration Device Family | EPC4, EPC8, EPC16 | — |
| Supported FPGA Family | Stratix II | — |
| Configuration Data Reload | Required after power-up, system initialization, or new configuration data request | — |
| Configuration Data Source | Nonvolatile external configuration memory | — |
| Target Device Technology | SRAM-based FPGA | — |
| Datasheet Source Page Count | 36 pages | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | — |
| 电源电压 | [DATA_NEEDED: supply voltage range] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface and pin assignments] | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF_DONE) |
| Programming Voltage | [DATA_NEEDED: programming voltage specification] | — |
| Maximum Configuration Clock | [DATA_NEEDED: maximum configuration clock frequency] | — |
| Junction Temperature | [DATA_NEEDED: junction temperature range] | — |
| Storage Temperature | [DATA_NEEDED: storage temperature range] | — |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL rating] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| 存储器类型 | — | Non-volatile Flash configuration PROM (in-system programmable) |
| Memory Density | — | 16 Mbit (2,097,152 x 8 bits) |
| Maximum DCLK Frequency | — | 33 MHz |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| 工作温度范围 | — | -40 C to +85 C (industrial) |
| In-System Programming | — | IEEE Std 1149.1 (JTAG) |
| Cascade Support | — | Yes (for higher density multi-PROM chains) |
| MSEL Compatibility | — | FPP / PS configuration modes (3.3 V legacy) |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Stratix, Stratix II, Stratix III, Stratix IV, Arria GX |
| Family Density Step | — | Largest member of EPC4 / EPC8 / EPC16 family |
| MSL 等级 | — | [DATA_NEEDED: MSL] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| Open-Drain nINIT_CONF_DONE | — | Yes |