EPC22LC20 vs EPC2LC20 对比
详细并排对比 EPC22LC20 出自 Intel 和 EPC2LC20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC22LC20 | EPC2LC20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.10 | $7.20 |
| 功能 | In-System Programmable Configuration PROM for SRAM-based FPGAs | — |
| 存储容量 | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | — |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | — |
| Supply Voltage - High Range | 4.75 V to 5.25 V | — |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| 封装 / 外壳 | 20-LCC (J-Lead, 9 x 9 mm) | — |
| 安装类型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| Packaging | Tube | — |
| 工作温度 | 0 C to +70 C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Minimum DC Input Voltage | -0.3 V | — |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | — |
| 存储器类型 | — | Non-volatile configuration PROM |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| 封装 | — | 20-pin PLCC (J-lead, 9x9 mm) |
| RoHS 状态 | — | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |