EPC2LC20 vs EPC1LC20-W 对比

详细并排对比 EPC2LC20 出自 Altera 和 EPC1LC20-W 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2LC20 EPC1LC20-W
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $7.20 $9.85
存储器类型 Non-volatile configuration PROM OTP (One-Time Programmable) Configuration PROM
存储容量 1.6 Mbit 1 Mbit
Configuration Interface Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE —
Programming Interface IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant —
Supply Voltage VCC 3.0 V to 3.6 V (3.3-V operation) —
ISP Voltage Range 5.0 V or 3.3 V —
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 —
Cascade Support Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams —
封装 20-pin PLCC (J-lead, 9x9 mm) 20-PLCC J-lead (9x9 mm)
安装类型 Surface Mount Surface Mount (PLCC socket or direct solder)
工作温度 -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] —
RoHS 状态 Non-Compliant (original Altera Pb-containing part) Compliant (Pb-free -W finish)
Lead-Free Version EPC2LC20N available as lead-free equivalent —
Programming Support Altera Programming Unit (APU), Quartus II, JTAG programmer —
Boundary-Scan IEEE 1149.1 compliant, 8-bit or 16-bit JTAG —
Configuration Clock (DCLK) — 8 MHz maximum
电源电压 — 3.3 V and 5.0 V
接口 — Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS)
In-System Programming — Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V
Lead Finish — Pb-free (matte tin) - "-W" suffix
Daisy-Chain Support — Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs
Compression Support — Yes - stores compressed Altera FPGA bitstreams
工作温度范围 — [DATA_NEEDED: operating temperature range]
Programming Cycles — 1 (OTP)
Target FPGA Families — Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury

数据手册与资源

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