EPC2LC20 vs EPC1LC20-W Comparação
Comparação detalhada lado a lado de EPC2LC20 por Altera e EPC1LC20-W por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC2LC20 | EPC1LC20-W |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | Memory ICs | Memory ICs |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,20 | $9,85 |
| Tipo de memória | Non-volatile configuration PROM | OTP (One-Time Programmable) Configuration PROM |
| Tamanho da memória | 1.6 Mbit | 1 Mbit |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| Encapsulamento | 20-pin PLCC (J-lead, 9x9 mm) | 20-PLCC J-lead (9x9 mm) |
| Tipo de montagem | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Temperatura de operação | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | — |
| Status RoHS | Non-Compliant (original Altera Pb-containing part) | Compliant (Pb-free -W finish) |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Tensão de alimentação | — | 3.3 V and 5.0 V |
| Interface | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Faixa de temperatura de operação | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |