EPC2LS20U vs EPC2L20U 对比
详细并排对比 EPC2LS20U 出自 Altera 和 EPC2L20U 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2LS20U | EPC2L20U |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | Memory ICs | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.25 | $10.55 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| 接口 | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| 封装 | 20-PLCC (J-lead, 9x9 mm) | 20-PLCC (PLCC-20) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| 工作温度 | [DATA_NEEDED: Operating Temperature] | -40C to +85C (industrial) |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | Yes (IEEE Std 1149.1 boundary scan) |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSL 等级 | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL level] |
| Compliance | RoHS (Pb-free per U suffix) | — |
| 存储容量 | — | 1.6 Mbit |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| 接口类型 | — | Serial configuration (DCLK/DATA0) |
| Programmability | — | In-system programmable via IEEE 1532 / JTAG |
| Supported FPGAs | — | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K |
| Configuration Mode | — | Single + Cascade (multi-PROM daisy chain) |
| Compression Support | — | Yes (FPGA decompresses bitstream) |
| 安装类型 | — | Surface Mount / Socket |
| 引脚数量 | — | 20 |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |