EPC2TC32UCAD48 vs EPC2TC32UCAF 对比

详细并排对比 EPC2TC32UCAD48 出自 Altera 和 EPC2TC32UCAF 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2TC32UCAD48 EPC2TC32UCAF
品牌 Altera Altera
分类 Memory ICs FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $10.40 $9.95
存储器类型 In-System Programmable Configuration PROM (Flash) —
Density 1.6 Mbit —
Configuration Clock 10 MHz max —
接口 Serial (AS) / Parallel (FPP, PS) / JTAG (IEEE 1149.1) —
电源电压 3.3 V (typical) —
Programmability In-system via JTAG (ISP), 100,000 erase/write cycles —
工作温度范围 -40 C to +85 C (industrial, U-suffix) —
封装 32-TQFP (7x7 mm, 0.8 mm pitch) 32-pin TQFP (CAF48), 7x7 mm
引脚数量 32 —
Cascade Support Yes (multi-device daisy-chain) —
Multi-Boot Support Yes (Altera remote system upgrade) —
Compatible FPGAs Altera Cyclone, Stratix, APEX, ACEX, Mercury families —
RoHS 状态 Compliant [DATA_NEEDED: RoHS compliance status]
Lead-Free Yes [DATA_NEEDED: lead-free status]
MSL 等级 3 (168 hours) [DATA_NEEDED: MSL rating]
Device Type — Configuration PROM (CPLD-style boot memory)
Memory Density — 1.6 Mbit
Supported FPGA Families — Altera APEX, Cyclone, Stratix, FLEX (LUT devices)
Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Logic Levels — 3.3 V / 2.5 V compatible
Configuration Interface — FLEX passive serial / passive parallel synchronous / passive parallel asynchronous
Programming Interface — IEEE 1149.1 (JTAG) in-system programmable
Daisy-Chain Support — Yes (via nCASC pin, multi-device FLEX chain)
Compression Support — Altera bitstream compression compatible
安装类型 — Surface Mount
工作温度 — [DATA_NEEDED: operating temperature range]
无卤 — [DATA_NEEDED: halogen-free status]

数据手册与资源

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