EPC4QC1C00N vs EPC4QC100T 对比
详细并排对比 EPC4QC1C00N 出自 Altera 和 EPC4QC100T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC4QC1C00N | EPC4QC100T |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.10 | $10.25 |
| Device Family | Enhanced Configuration Device (EPC4) | — |
| Memory Density | 4 Mbit (4,194,304 bits) | 4 Mbit |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V (3.3 V typ) |
| I/O Voltage Tolerance | 3.3 V / 5 V tolerant | — |
| Interface to FPGA | Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE | — |
| Configuration Data Width | 4-bit multiplexed on single DATA pin | — |
| 封装 | 100-pin PQFP (QFP-100) | 100-pin PQFP (Plastic Quad Flat Pack), 20 x 14 mm |
| 工作温度 | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| In-System Programming | JTAG (IEEE 1149.1) | IEEE 1149.1 JTAG + serial interface |
| Programming Voltage | On-chip generated, no external VPP | — |
| Page Mode | Yes, multi-page storage supported | — |
| Target FPGA Families | Stratix, Cyclone, APEX, Mercury, ACEX | — |
| Configuration Clock (DCLK) | [DATA_NEEDED: DCLK max frequency] | — |
| MSL 等级 | 3 (per JEDEC J-STD-020) | 3 (per JEDEC J-STD-020) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| 存储器类型 | — | Flash configuration PROM (non-volatile) |
| Configuration Interface | — | Serial / x8 Parallel (selectable) |
| Maximum Serial Clock Frequency | — | 66 MHz |
| Supported FPGAs | — | Altera/Intel Cyclone, Stratix, APEX families |
| I/O Voltage (VCCIO / MultiVolt) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| JTAG Support | — | Yes (1149.1 boundary-scan compliant) |
| Configuration Modes | — | Serial (1-bit) and Parallel (x8) |
| Daisy-Chain Support | — | Yes (EPC4-to-EPC4 only) |
| 安装类型 | — | Surface Mount |
| Lead-Free / RoHS | — | Lead-free; RoHS compliance depends on date code |