EPF10K130EBC356-1 vs EPF10K130EBC356-1N 对比

详细并排对比 EPF10K130EBC356-1 出自 Altera 和 EPF10K130EBC356-1N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF10K130EBC356-1 EPF10K130EBC356-1N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $95.00 $18.20
Series FLEX 10KE —
Device Family FLEX-10KE Field Programmable Gate Array —
Typical Gate Count 130,000 gates —
Logic Elements (LEs) 6,656 6,656
Embedded Memory (EABs) 65,536 bits (8 Kbyte) / 12 EABs —
Logic Array Blocks (LABs) 832 —
Maximum User I/O 274 —
Maximum Operating Frequency 333 MHz —
Propagation Delay 0.6 ns 0.6 ns
Core Voltage 2.5 V —
I/O Voltage 3.3 V (5 V tolerant) —
Logic Family CMOS CMOS
Process Technology 0.22 µm SRAM 0.22 µm
封装 356-LBGA (35x35 mm) 356-LBGA
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (Commercial) 0 °C to 70 °C (Commercial)
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel —
Family — FLEX 10KE
Typical Gates — 130,000
Maximum System Gates — [DATA_NEEDED: maximum system gates for EPF10K130E]
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count for EPF10K130E]
Total RAM Bits — 65,536
User I/O Pins — 274
Package Code — LBGA
Core Supply Voltage — 2.5 V
I/O Supply Voltage — 3.3 V
Speed Grade — -1
Maximum Internal Frequency — 333.33 MHz
JTAG Boundary-Scan — IEEE Std. 1149.1-1990 compliant
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V)
RoHS 状态 — [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N]

数据手册与资源

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