EPF10K250EFI672-3 vs EPF10K250EFC672-2 对比

详细并排对比 EPF10K250EFI672-3 出自 Intel 和 EPF10K250EFC672-2 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF10K250EFI672-3 EPF10K250EFC672-2
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $125.00 $108.00
Family FLEX 10KE FLEX 10KE
Typical Gates 250,000 250,000
Logic Elements [DATA_NEEDED: exact LE count] 12,480
User I/O Pins 470 —
Embedded Array Blocks (EABs) 12 20
EAB Dual-Port Width Up to 16-bit —
Maximum EAB Memory [DATA_NEEDED: bits per EAB] —
Propagation Delay (tpd) 0.4 ns (typical, -3 speed grade) —
Core Supply Voltage 2.5 V 2.3 V (typical 2.5 V)
I/O Supply Voltage 2.5 V / 3.3 V (multiVolt I/O) —
封装 672-ball FineLine BGA, 1.27 mm pitch 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Process Technology CMOS, SRAM-based configuration —
Configuration Interface JTAG / ByteBlaster (EPC2/EPC8 PROM) —
工作温度 0 °C to 70 °C (commercial) 0 C to +70 C (Commercial)
Design Entry EDIF 2 0 0 / 3 0 0, LPM, VHDL, Verilog —
RoHS 状态 Unknown (legacy Altera non-RoHS device) Non-RoHS Compliant (per Fly-Wing listing)
Maximum User RAM Bits — 40,960
User I/Os — 470
引脚数量 — 672
Propagation Delay — 0.4 ns
I/O Standard Support — 1.8 V, 2.5 V, 3.3 V (multi-volt I/O)
Logic Family — CMOS, SRAM-based
Configuration — SRAM, in-system programmable (ISP) via JTAG
Boundary Scan — IEEE 1149.1 (JTAG) compliant
安装类型 — Surface Mount

数据手册与资源

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