EPF10K50GC403-4 vs EPF10K50GC403-3 对比

详细并排对比 EPF10K50GC403-4 出自 Altera 和 EPF10K50GC403-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPF10K50GC403-3 EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 Obsolete

规格对比

参数 EPF10K50GC403-4 EPF10K50GC403-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $62.00 $68.00
Family FLEX 10KA FLEX 10K
Logic Elements 2,880 —
Typical Gates 50,000 —
Embedded Array Blocks (EABs) 20 Yes (per datasheet)
Maximum Internal Clock Frequency 125 MHz —
Speed Grade -4 -3
Process Technology 0.42 µm CMOS SRAM 0.42 µm CMOS
电源电压 4.75 V to 5.25 V (5 V nominal) —
I/O Standards 3.3 V or 5 V configurable (multiVolt) —
封装 403-pin CPGA (Ceramic Pin Grid Array) 403-pin CPGA
安装类型 Through-hole (CPGA) —
Configuration Memory SRAM (in-system programmable) —
Boundary Scan IEEE 1149.1 (JTAG) —
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Compliant (per Kjr Technology listing)
Typical Gate Count — 50,000 gates
Logic Elements (Cells) — 2,880
Maximum Operating Frequency — 125 MHz
Core Supply Voltage — 5 V
I/O Supply Voltage — 3.3 V or 5 V (MultiVolt)
Logic Array Blocks (LABs) — Yes (per datasheet)
JTAG Boundary Scan — IEEE Std 1149.1 (per family datasheet)
Configuration Method — SRAM-based, external configuration device required

数据手册与资源

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