EPF10K50VRC240-2 vs EPF10K50VRC240-1 对比

详细并排对比 EPF10K50VRC240-2 出自 Intel 和 EPF10K50VRC240-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF10K50VRC240-2 EPF10K50VRC240-1
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $18.95 $130.32
Family Flex 10K FLEX 10K
Logic Cells 2,880 —
Typical Gates 50,000 50,000
Logic Elements (LEs) 20,480 —
Logic Array Blocks (LABs) 360 —
User I/Os 189 —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count and RAM bits] —
Maximum Internal Frequency 125 MHz —
Propagation Delay 0.6 ns 0.6 ns
Process Technology 0.42 µm CMOS 0.42 µm CMOS
Core Supply Voltage 3.3 V —
Speed Grade -2 (mid) —
封装 240-pin RQFP / HFQFP (exposed pad), gull-wing 240-RQFP Exposed Pad
安装类型 Surface Mount Surface Mount
工作温度 0 °C to +70 °C (commercial) 0 °C to +70 °C (Commercial)
Configuration Memory SRAM (volatile, external PROM required) —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant
Logic Elements — 2,880
Embedded Memory — 20,480 bits (189 Kb)
User I/O — 274 (max)
Number of I/O Pins — 189
Pins — 240
Core Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — MultiVolt (2.5 V / 3.3 V / 5 V tolerant)
Internal Frequency (max) — 66.67 MHz
Logic Family — CMOS
JTAG Support — Yes (IEEE Std 1149.1-1990)
Configuration Interface — JTAG / BitBlaster / ByteBlasterMV / Jam STAPL
Programming Language — Altera MAX+PLUS II / Quartus

数据手册与资源

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