EPM1270F256I5 vs EPM1270F256C5 对比
详细并排对比 EPM1270F256I5 出自 Altera 和 EPM1270F256C5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM1270F256I5 | EPM1270F256C5 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.90 | $25.40 |
| Device Family | MAX II | — |
| Series | EPM1270 | MAX II |
| Macrocell Count | 980 | — |
| Logic Elements | 1270 | — |
| User I/O Pins | 212 (max) | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| 封装 | 256-ball FBGA (FineLine BGA) | 256-ball FineLine BGA (FBGA-256) |
| Pin/Package Count | 256 | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Pin-to-Pin Delay (tPD) | 6.2 ns | — |
| 工作温度 | -40 °C to +100 °C (industrial, "I") | 0 °C to +85 °C (commercial, 'C' grade) |
| Speed Grade | 5 | — |
| 安装类型 | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP via ByteBlaster / USB-Blaster |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Compliant |
| Family | — | EPM1270 |
| Macro Cells | — | 980 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Logic Delay (tPD) | — | 6.2 ns (C5 speed grade) |
| Internal Operating Frequency | — | 201.1 MHz |
| Core Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | LVCMOS/LVTTL 1.8 V, 2.5 V, 3.3 V, 5.0 V (MultiVolt) |
| Configuration Memory | — | On-chip flash (non-volatile, instant-on) |