EPM240GT100C5N vs EPM240GT100I5N 对比

详细并排对比 EPM240GT100C5N 出自 Altera 和 EPM240GT100I5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM240GT100C5N EPM240GT100I5N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $9.20 $6.31
Family MAX II MAX II
Series EPM240 —
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements (LEs) 240 240
Macrocells 192 —
User I/Os 80 80
Pin-to-Pin Delay (tPD) 4.7 ns —
User Flash Memory (UFM) 8 Kbits —
Core Supply Voltage (VCCINT) 2.5 V or 3.3 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
工作温度 0C to +85C (Commercial) -40 °C to +100 °C (Industrial)
封装 100-pin TQFP (T100) 100-pin TQFP (14x14 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount
Programmable Type In-System Programmable (ISP) via JTAG —
Configuration Memory Non-volatile Flash (instant-on) —
MSL 等级 3 —
RoHS 状态 Compliant —
Product Type — CPLD (Complex Programmable Logic Device)
Equivalent Macrocells — 192
Propagation Delay (tPD) — 4.7 ns
Internal Performance (fMAX) — 304 MHz
Embedded Non-Volatile Memory — 8 Kbits user Flash
Process Technology — 0.18 µm 6-layer-metal Flash CMOS
Supply Voltage - Core (VCCINT) — 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant)
I/O Bank Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O
Programming Interface — JTAG (IEEE 1149.1) ISP
Lead-Free / RoHS — Yes (suffix N)

数据手册与资源

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