EPM3032ALC44-4 vs EPM3032ALC44-10N 对比
详细并排对比 EPM3032ALC44-4 出自 Altera 和 EPM3032ALC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3032ALC44-4 | EPM3032ALC44-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1.10 | $0.94 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | 34 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | — |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | — |
| 封装 | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead, surface mount) |
| 工作温度 | 0°C to +70°C (Commercial) | [DATA_NEEDED: industrial/commercial range] |
| Technology | CMOS EEPROM-based | CMOS EEPROM-based |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: compliant or non-compliant] |
| 安装类型 | Surface Mount (PLCC J-Lead) | Surface Mount |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 600 gates |
| Propagation Delay (tPD) | — | 10 ns |
| Internal fMAX | — | 103.1 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| In-System Programmability | — | Yes, via IEEE 1149.1 JTAG |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes, IEEE 1149.1 compliant |