EPM3064ALI44-10N vs EPM3064ALC44-10N 对比

详细并排对比 EPM3064ALI44-10N 出自 Altera 和 EPM3064ALC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ALI44-10N EPM3064ALC44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $7.80 $4.25
Series MAX 3000A —
Programmable Type In System Programmable (ISP) —
Number of Macrocells 64 —
Number of I/O 34 —
Logic Gates 1250 gates —
Number of Logic Elements/Blocks 4 LABs —
Propagation Delay (tPD) 10 ns (speed grade -10) 10 ns
Counter Frequency up to 227.3 MHz —
Supply Voltage - Core 3.3 V —
I/O Logic Level Support 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programming Interface IEEE Std. 1149.1 JTAG —
工作温度 -40 C to +85 C (Industrial) [DATA_NEEDED: commercial / industrial grade]
封装 44-pin PLCC (J-Lead) 44-pin PLCC (LC44)
安装类型 Surface Mount (socketable PLCC) Surface Mount (PLCC socket compatible)
Lead Free / RoHS Status Lead Free, RoHS Compliant —
Hot-Socketing Support Yes —
Configuration Memory CMOS EEPROM (non-volatile) CMOS EEPROM
Product Family — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 4
User I/O Pins — 34
Usable Gates — 1,250
Maximum Counter Frequency — 227.3 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
I/O Bank Voltage (VCCIO) — 3.0 V to 3.6 V (MultiVolt)
In-System Programmability — Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant)
RoHS 状态 — Compliant
Open-Drain Output Option — Yes (per I/O pin)
Output Slew-Rate Control — Programmable

数据手册与资源

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