EPM3064ATC44-10 vs EPM3064ATC44-10N 对比

详细并排对比 EPM3064ATC44-10 出自 Altera 和 EPM3064ATC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 量产中

规格对比

参数 EPM3064ATC44-10 EPM3064ATC44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $4.35 $5.10
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 1250
Number of Logic Blocks / LABs 4 LABs —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 227.3 MHz (counter speed) —
Programmable I/Os 34 —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) 3.3 V
I/O Bank Voltage (VCCIO) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Technology CMOS EEPROM, 5 V tolerant I/O —
In-System Programming IEEE Std. 1532 (JTAG) IEEE Std. 1532 compliant
Boundary-Scan Support IEEE 1149.1 (JTAG) —
封装 TQFP-44, 10 x 10 mm, 0.8 mm pitch TQFP-44 (10x10 mm)
安装类型 Surface Mount Surface Mount
工作温度范围 0C to +70C (commercial) —
RoHS 状态 Non-compliant (legacy Altera, Pb-bearing) Compliant
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
User I/O Pins — 34
Logic Array Blocks (LABs) — 4
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency — 192.3 MHz
I/O Standard — MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
Configuration Memory — EEPROM (non-volatile)
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG) compliant
工作温度 — 0C to +70C (commercial)
Pin-Locking — Yes (across design iterations)

数据手册与资源

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