EPM3064ATI44-10NAD vs EPM3064ATC44-10N 对比

详细并排对比 EPM3064ATI44-10NAD 出自 Altera 和 EPM3064ATC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 量产中

规格对比

参数 EPM3064ATI44-10NAD EPM3064ATC44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $4.10 $5.10
Family MAX 3000A MAX 3000A
Macrocells 64 —
Usable Gates 1,250 1250
Logic Array Blocks (LABs) 4 (16 macrocells each) 4
User I/Os (max) 34 —
Pin-to-Pin Delay (tPD) 10 ns 10 ns
Setup Time (tSU) 4.5 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V or 2.5 V —
封装 TQFP-44 TQFP-44 (10x10 mm)
工作温度 -40C to +85C (Industrial) 0C to +70C (commercial)
Programming Interface JTAG (IEEE Std. 1532 compliant) —
In-System Programmable Yes —
RoHS 状态 Compliant Compliant
安装类型 Surface Mount Surface Mount
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
User I/O Pins — 34
Maximum Counter Frequency — 192.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Standard — MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
Configuration Memory — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG) compliant
Pin-Locking — Yes (across design iterations)

数据手册与资源

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