EPM3064ATI44-10NAD vs EPM3064ATC44-10N Comparison

Detailed side-by-side comparison of EPM3064ATI44-10NAD by Altera and EPM3064ATC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATI44-10NAD EPM3064ATC44-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $4.10 $5.10
Family MAX 3000A MAX 3000A
Macrocells 64 β€”
Usable Gates 1,250 1250
Logic Array Blocks (LABs) 4 (16 macrocells each) 4
User I/Os (max) 34 β€”
Pin-to-Pin Delay (tPD) 10 ns 10 ns
Setup Time (tSU) 4.5 ns β€”
Core Voltage (VCCINT) 3.3 V β€”
I/O Voltage (VCCIO) 3.3 V or 2.5 V β€”
Package TQFP-44 TQFP-44 (10x10 mm)
Operating Temperature -40C to +85C (Industrial) 0C to +70C (commercial)
Programming Interface JTAG (IEEE Std. 1532 compliant) β€”
In-System Programmable Yes β€”
RoHS Status Compliant Compliant
Mounting Type Surface Mount Surface Mount
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
User I/O Pins β€” 34
Maximum Counter Frequency β€” 192.3 MHz
Supply Voltage (VCCINT) β€” 3.3 V
I/O Standard β€” MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
Configuration Memory β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1532 compliant
Boundary-Scan Test β€” IEEE Std. 1149.1 (JTAG) compliant
Pin-Locking β€” Yes (across design iterations)

Datasheets & Resources

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