EPM3128ATC100-5N vs EPM3128ATC100-10N 对比

详细并排对比 EPM3128ATC100-5N 出自 Intel 和 EPM3128ATC100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC100-5N EPM3128ATC100-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $8.20 $5.20
Device Family MAX 3000A —
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 —
Logic Array Blocks (LABs) 8 (16 macrocells each) —
Usable Gates Up to 10,000 2500
User I/Os 80 —
Propagation Delay (tPD) 5 ns 10 ns
Maximum Internal Frequency 192.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
Programming Technology EEPROM (non-volatile) —
In-System Programmability Yes (IEEE Std. 1532) —
JTAG Boundary Scan Yes (IEEE 1149.1) —
封装 TQFP-100 (TC100) 100-pin TQFP (14 x 14 x 1.0 mm)
工作温度 0 C to +70 C (commercial) 0 °C to +70 °C (commercial)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant
Family — MAX 3000A
Macro Cells — 128
Number of I/O — 80
Logic Elements / Blocks — 8 LABs (16 macrocells each)
Maximum Internal Frequency (fMAX) — 98 MHz
Supply Voltage VCCINT — 3.3 V
I/O Bank Voltage VCCIO — 3.3 V or 2.5 V (selectable)
Configuration Memory — CMOS EEPROM (non-volatile, instant-on)
In-System Programming — IEEE Std. 1532-compliant ISP via JTAG
Lead-Free — Yes
MSL 等级 — 3 (per JEDEC J-STD-020)

数据手册与资源

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