EPM3128ATC144-10N - 128-Macro MAX 3000A CPLD, 144-TQFP | Intel
料号： EPM3128ATC144-10N ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $10.94 | $10.94 |
| 10 | $9.85 | $98.50 |
| 100 | $8.75 | $875.00 |
| 500 | $7.66 | $3,830.00 |
| 1,000 | $6.56 | $6,560.00 |
EPM3128ATC144-10N 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks with a centralized interconnect matrix. CPLDs sit between simple SPLDs/PALs and FPGAs in the programmable-logic hierarchy, offering deterministic timing (fixed pin-to-pin delay), instant-on EEPROM configuration, and simple integration of glue logic, state machines, and bus interfaces. MAX 3000A devices target low-cost, high-volume glue-logic, interface bridging, and bus-decoding applications where predictable timing and ISP convenience outweigh the density of an FPGA.
Key features of the EPM3128ATC144-10N include 128 macrocells organized into 8 Logic Array Blocks (LABs), a MultiVolt I/O interface that supports 3.3 V, 2.5 V, and 1.8 V logic levels on the same device, built-in boundary-scan test (BST) circuitry compliant with IEEE 1149.1 (JTAG), and ISP circuitry compliant with IEEE 1532. The architecture also provides four pin-locked JTAG instructions, JTAG-based in-system programming, and an open-drain or programmable pull-up option on every I/O pin.
The MAX 3000A architecture uses EEPROM-based configuration cells, allowing instant-on behavior at power-up with no external configuration memory. Each macrocell contains a programmable AND/OR array, a flip-flop with selectable clear/clock/preset, and a wide range of product-term allocation options including parallel expanders and shareable expanders. The global interconnect matrix provides predictable, fixed-delay paths from any I/O pin to any macrocell — a key advantage over SRAM-based FPGAs in real-time control loops.
Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microcontroller-to-peripheral glue), address decoding and chip-select generation, power-sequencing logic, state-machine replacement for discrete 74-series logic, and JTAG-based board-level test integration. The wide MultiVolt I/O range also makes the part attractive as a level shifter between 5 V legacy devices and 3.3 V/1.8 V processors.
When designing with this device, allocate I/O pins carefully during logic synthesis to avoid routing congestion and respect the 96-user-I/O limit when assigning bank-level voltage references. Decoupling should follow the MAX 3000A reference design: a 0.1 µF ceramic capacitor on every VCCIO bank pin placed within 5 mm of the package, with one bulk 10 µF tantalum or ceramic cap on the VCCINT rail.
This page synthesizes verified distributor pricing, same-package drop-in alternatives, and practical design notes that complement the manufacturer datasheet.
直接替换替代料： EPM3128ATC144-10N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM3128ATC144-10N （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, RoHS Status, Usable Gates, Propagation Delay (tPD).
快速对比工具——选择替代料号进行并排对比：
EPM3128ATC144-10
✅ 直接替换✓ 有现货
$6.2 / 个
查看数据手册 →EPM3128ATC144-7N
✅ 直接替换✓ 有现货
$9.25 / 个
查看数据手册 →EPM3128ATC144-5N
✅ 直接替换✓ 有现货
$13.75 / 个
查看数据手册 →EPM3128ATI144-10N
✅ 直接替换✓ 有现货
$10.32 / 个
查看数据手册 →EPM3128ATC144-10N 最大额定值与电气特性
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 (up to 10,000 for full family) |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 96 |
| Propagation Delay (tPD) | 10 ns (speed grade -10) |
| Counter Frequency (fCNT) | 98 MHz |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V |
| MultiVolt I/O Support | 3.3 V / 2.5 V / 1.8 V |
| Configuration Memory | EEPROM (in-system programmable, non-volatile) |
| 封装 | 144-pin TQFP |
| 安装类型 | Surface Mount |
| 工作温度 | 0 °C to +70 °C (commercial) |
| JTAG (IEEE 1149.1) | Yes (BST + pin-locking) |
| ISP (IEEE 1532) | Yes |
EPM3128ATC144-10N 引脚配置
| 引脚 1 | I/O — User I/O (bank 1) — multi-volt 3.3 V / 2.5 V / 1.8 V |
| 引脚 2 | I/O — User I/O (bank 1) |
| 引脚 3 | I/O — User I/O (bank 1) |
| 引脚 4 | I/O — User I/O (bank 1) |
| 引脚 5 | VCCINT — Core 3.3 V supply |
| 引脚 6 | I/O — User I/O (bank 1) |
| 引脚 7 | I/O — User I/O (bank 1) |
| 引脚 8 | I/O — User I/O (bank 1) |
| 引脚 9 | I/O — User I/O (bank 1) |
| 引脚 10 | GND — Ground |
| 引脚 11 | I/O — User I/O (bank 1) |
| 引脚 12 | I/O — User I/O (bank 1) |
| 引脚 13 | I/O — User I/O (bank 1) |
| 引脚 14 | I/O — User I/O (bank 2) |
| 引脚 15 | I/O — User I/O (bank 2) |
| 引脚 16 | VCCIO1 — I/O bank 1 reference supply (3.3 / 2.5 / 1.8 V) |
| 引脚 17 | I/O — User I/O (bank 2) |
| 引脚 18 | I/O — User I/O (bank 2) |
| 引脚 19 | I/O — User I/O (bank 2) |
| 引脚 20 | I/O — User I/O (bank 2) |
| 引脚 21 | I/O — User I/O (bank 2) |
| 引脚 22 | GND — Ground |
| 引脚 23 | I/O — User I/O (bank 2) |
| 引脚 24 | I/O — User I/O (bank 2) |
| 引脚 25 | I/O — User I/O (bank 2) |
| 引脚 26 | I/O — User I/O (bank 2) |
| 引脚 27 | I/O — User I/O (bank 2) |
| 引脚 28 | VCCIO2 — I/O bank 2 reference supply |
| 引脚 29 | I/O — User I/O (bank 2) |
| 引脚 30 | I/O — User I/O (bank 2) |
| 引脚 31 | I/O — User I/O (bank 2) |
| 引脚 32 | I/O — User I/O (bank 2) |
| 引脚 33 | I/O — User I/O (bank 2) |
| 引脚 34 | GND — Ground |
| 引脚 35 | I/O — User I/O (bank 3) |
| 引脚 36 | I/O — User I/O (bank 3) |
| 引脚 37 | I/O — User I/O (bank 3) |
| 引脚 38 | I/O — User I/O (bank 3) |
| 引脚 39 | I/O — User I/O (bank 3) |
| 引脚 40 | VCCIO3 — I/O bank 3 reference supply |
| 引脚 41 | I/O — User I/O (bank 3) |
| 引脚 42 | I/O — User I/O (bank 3) |
| 引脚 43 | I/O — User I/O (bank 3) |
| 引脚 44 | I/O — User I/O (bank 3) |
| 引脚 45 | I/O — User I/O (bank 3) |
| 引脚 46 | GND — Ground |
| 引脚 47 | I/O — User I/O (bank 3) |
| 引脚 48 | I/O — User I/O (bank 3) |
| 引脚 49 | I/O — User I/O (bank 3) |
| 引脚 50 | I/O — User I/O (bank 3) |
| 引脚 51 | I/O — User I/O (bank 3) |
| 引脚 52 | VCCIO4 — I/O bank 4 reference supply |
| 引脚 53 | I/O — User I/O (bank 4) |
| 引脚 54 | I/O — User I/O (bank 4) |
| 引脚 55 | I/O — User I/O (bank 4) |
| 引脚 56 | I/O — User I/O (bank 4) |
| 引脚 57 | I/O — User I/O (bank 4) |
| 引脚 58 | GND — Ground |
| 引脚 59 | I/O — User I/O (bank 4) |
| 引脚 60 | I/O — User I/O (bank 4) |
| 引脚 61 | I/O — User I/O (bank 4) |
| 引脚 62 | I/O — User I/O (bank 4) |
| 引脚 63 | I/O — User I/O (bank 4) |
| 引脚 64 | VCCINT — Core 3.3 V supply |
| 引脚 65 | I/O — User I/O (bank 4) |
| 引脚 66 | I/O — User I/O (bank 4) |
| 引脚 67 | I/O — User I/O (bank 4) |
| 引脚 68 | I/O — User I/O (bank 4) |
| 引脚 69 | GND — Ground |
| 引脚 70 | TDI — JTAG Test Data In (pin-locked, IEEE 1149.1) |
| 引脚 71 | TMS — JTAG Test Mode Select (pin-locked, IEEE 1149.1) |
| 引脚 72 | TCK — JTAG Test Clock (pin-locked, IEEE 1149.1) |
| 引脚 73 | TDO — JTAG Test Data Out (pin-locked, IEEE 1149.1) |
| 引脚 74 | I/O — User I/O (bank 1) |
| 引脚 75 | I/O — User I/O (bank 1) |
| 引脚 76 | I/O — User I/O (bank 1) |
| 引脚 77 | I/O — User I/O (bank 1) |
| 引脚 78 | VCCINT — Core 3.3 V supply |
| 引脚 79 | I/O — User I/O (bank 1) |
| 引脚 80 | I/O — User I/O (bank 1) |
| 引脚 81 | I/O — User I/O (bank 1) |
| 引脚 82 | I/O — User I/O (bank 1) |
| 引脚 83 | I/O — User I/O (bank 1) |
| 引脚 84 | GND — Ground |
| 引脚 85 | I/O — User I/O (bank 1) |
| 引脚 86 | I/O — User I/O (bank 1) |
| 引脚 87 | I/O — User I/O (bank 1) |
| 引脚 88 | I/O — User I/O (bank 2) |
| 引脚 89 | I/O — User I/O (bank 2) |
| 引脚 90 | VCCIO1 — I/O bank 1 reference supply |
| 引脚 91 | I/O — User I/O (bank 2) |
| 引脚 92 | I/O — User I/O (bank 2) |
| 引脚 93 | I/O — User I/O (bank 2) |
| 引脚 94 | I/O — User I/O (bank 2) |
| 引脚 95 | I/O — User I/O (bank 2) |
| 引脚 96 | GND — Ground |
| 引脚 97 | I/O — User I/O (bank 2) |
| 引脚 98 | I/O — User I/O (bank 2) |
| 引脚 99 | I/O — User I/O (bank 2) |
| 引脚 100 | I/O — User I/O (bank 2) |
| 引脚 101 | I/O — User I/O (bank 2) |
| 引脚 102 | VCCIO2 — I/O bank 2 reference supply |
| 引脚 103 | I/O — User I/O (bank 2) |
| 引脚 104 | I/O — User I/O (bank 2) |
| 引脚 105 | I/O — User I/O (bank 2) |
| 引脚 106 | I/O — User I/O (bank 2) |
| 引脚 107 | I/O — User I/O (bank 2) |
| 引脚 108 | GND — Ground |
| 引脚 109 | I/O — User I/O (bank 3) |
| 引脚 110 | I/O — User I/O (bank 3) |
| 引脚 111 | I/O — User I/O (bank 3) |
| 引脚 112 | I/O — User I/O (bank 3) |
| 引脚 113 | I/O — User I/O (bank 3) |
| 引脚 114 | VCCIO3 — I/O bank 3 reference supply |
| 引脚 115 | I/O — User I/O (bank 3) |
| 引脚 116 | I/O — User I/O (bank 3) |
| 引脚 117 | I/O — User I/O (bank 3) |
| 引脚 118 | I/O — User I/O (bank 3) |
| 引脚 119 | I/O — User I/O (bank 3) |
| 引脚 120 | GND — Ground |
| 引脚 121 | I/O — User I/O (bank 3) |
| 引脚 122 | I/O — User I/O (bank 3) |
| 引脚 123 | I/O — User I/O (bank 3) |
| 引脚 124 | I/O — User I/O (bank 4) |
| 引脚 125 | I/O — User I/O (bank 4) |
| 引脚 126 | VCCIO4 — I/O bank 4 reference supply |
| 引脚 127 | I/O — User I/O (bank 4) |
| 引脚 128 | I/O — User I/O (bank 4) |
| 引脚 129 | I/O — User I/O (bank 4) |
| 引脚 130 | I/O — User I/O (bank 4) |
| 引脚 131 | I/O — User I/O (bank 4) |
| 引脚 132 | GND — Ground |
| 引脚 133 | I/O — User I/O (bank 4) |
| 引脚 134 | I/O — User I/O (bank 4) |
| 引脚 135 | I/O — User I/O (bank 4) |
| 引脚 136 | I/O — User I/O (bank 4) |
| 引脚 137 | I/O — User I/O (bank 4) |
| 引脚 138 | VCCINT — Core 3.3 V supply |
| 引脚 139 | I/O — User I/O (bank 4) |
| 引脚 140 | I/O — User I/O (bank 4) |
| 引脚 141 | I/O — User I/O (bank 4) |
| 引脚 142 | I/O — User I/O (bank 4) |
| 引脚 143 | GND — Ground |
| 引脚 144 | I/O — User I/O (bank 4) |
典型应用
EPM3128ATC144-10N 适用于 6 应用s: Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Power-Sequencing Logic, Legacy Logic Replacement (74-Series Consolidation), JTAG-Based Board Test Integration, Industrial Control and I/O Expansion.
Bus-Interface Glue Logic
The EPM3128ATC144-10N is ideally suited as bus-interface glue logic between microcontrollers, ASICs, and peripherals. Its 128 macrocells and 96 user I/Os can decode multiple address ranges and generate chip selects for memories, sensors, and bus peripherals in parallel. The 10 ns pin-to-pin propagation delay is well below typical bus-cycle budgets, ensuring that address-decoded strobes arrive before the next cycle. Combined with deterministic fixed-delay routing and instant-on EEPROM, the part replaces stacks of 74-series glue logic with a single re-programmable device.
推荐
Address Decoding and Chip-Select Generation
The MAX 3000A wide AND-OR array makes the EPM3128ATC144-10N well matched to address-decoding and chip-select generation tasks. Each macrocell can implement a product-term-rich decode equation across up to 36 inputs, ideal for partitioning a 24-bit or 32-bit address bus into multiple chip-select outputs. The 96 user I/Os comfortably host the address inputs plus the dozen or more decoded outputs. JTAG-based in-system programming means decode maps can be updated on the production line without re-spinning the board.
推荐
Power-Sequencing Logic
The EPM3128ATC144-10N is widely used as power-sequencing logic in multi-rail systems. Its MultiVolt I/O (3.3 V / 2.5 V / 1.8 V) lets one device interface with rails of mixed voltage, while the 3.3 V core runs from a fixed supply. Programmable macrocells can implement delay lines, fault-timeout counters, and Power-Good fan-out logic, replacing dedicated sequencer ICs. Deterministic tPD guarantees that enable signals arrive in the correct order without race conditions.
推荐
Legacy Logic Replacement (74-Series Consolidation)
The EPM3128ATC144-10N is a classic choice for replacing dozens of 74HC/74AHC/74LVT SSI/MSI gates with a single re-programmable device. With 128 macrocells, each implementing 4 to 16 product terms, it can substitute 20–40 equivalent 7400-series packages, reducing board area, BOM count, and inventory overhead. The 144-pin TQFP provides enough user I/O for multi-channel replacements. Designers port legacy gate-level schematics into Altera/Intel MAX+PLUS II or Quartus using direct gate-equivalent primitives.
推荐
JTAG-Based Board Test Integration
The integrated IEEE 1149.1 boundary-scan test (BST) circuitry and JTAG-compliant ISP interface make the EPM3128ATC144-10N valuable for board-level test integration. It can act as a JTAG bridge or be daisy-chained with other boundary-scan devices on the PCB, enabling cluster testing of non-BST parts via pin-locking and interconnect test vectors. The IEEE 1532-compliant ISP interface also allows the CPLD itself to be re-flashed in-circuit through the same JTAG chain used for boundary scan.
推荐
Industrial Control and I/O Expansion
With its 96 user I/Os and deterministic timing, the EPM3128ATC144-10N is well suited to industrial control applications such as PLC I/O expansion, encoder interfacing, and stepper-motor pulse-train generation. Industrial-temperature variants (EPM3128ATI144-10N) extend operation to -40 °C to +85 °C. The 10 ns tPD enables deterministic sub-microsecond response times for safety and control loops. MultiVolt I/O also simplifies interface to 1.8 V or 2.5 V sensors without external level shifters.
推荐
推荐产品汇总
工程参考数据： EPM3128ATC144-10N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATC144-5N | EPM3128ATI144-10N |
|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP — same | 144-pin TQFP — same | 144-pin TQFP — same | 144-pin TQFP — same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Speed Grade (tPD) | 10 ns | 10 ns (same) | 7.5 ns (faster) | 5 ns (faster) | 10 ns (same) |
| Counter Frequency (fCNT) | 98 MHz | 98 MHz | 125 MHz | 152 MHz | 98 MHz |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C (industrial) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead Finish (RoHS) | Pb-free / RoHS (N suffix) | Legacy lead finish (non-N) | Pb-free / RoHS | Pb-free / RoHS | Pb-free / RoHS |
| User I/Os | 96 | 96 | 96 | 96 | 96 |
关键差异点
- Industrial temperature variant on the same die （对比 EPM3128ATC144-10)
- Faster -7 speed grade in the same package （对比 EPM3128ATC144-7N)
- Faster -5 speed grade available for highest-performance designs （对比 EPM3128ATC144-5N)
设计说明
Estimated: The EPM3128ATC144-10N draws roughly 50–80 mA of Icc from a 3.3 V VCCINT supply in typical 50 MHz-use cases with all 96 I/Os switching at 25 MHz. Each VCCINT pin (5–7 pins on this 144-TQFP) and each VCCIO pin must have a dedicated 0.1 µF X7R ceramic decoupling capacitor placed within 5 mm of the package pin, with one bulk 10 µF tantalum or ceramic capacitor per rail shared across the board. Failure to decouple each bank independently can cause VCCIO rail collapse during simultaneous switching of output-enable toggles.
Use a 4-layer PCB with continuous ground and power planes under the 144-pin TQFP footprint. Route high-speed JTAG signals (TCK, TMS, TDI, TDO) as 50 Ω microstrip or stripline with ground reference, keeping total JTAG chain stub length below 50 mm. For MultiVolt banks, route each VCCIO reference pin to an island on the power plane and avoid stitching signals across I/O-bank boundaries, which can introduce ground-bounce noise on adjacent I/Os.
Do not assume 5 V tolerance — the EPM3128ATC144-10N I/O pins are not 5 V-tolerant. Driving any user I/O above the VCCIO rail (3.3 V max) or below ground will inject latch-up current through the I/O clamp diodes; use external 74LVC245 or 74AVC series level-shifters for 5 V interfacing. Also, JTAG pins TCK/TMS/TDI/TDO are pin-locked and cannot be repurposed as user I/O even when JTAG is disabled in software. Confirm pin allocation in the Quartus or MAX+PLUS II pin-planner before fab.
For output-edge rates exceeding 5 ns into 50 pF loads, place a 22–33 Ω series damping resistor near each high-speed output to reduce ground-bounce and undershoot. Synchronous output-enable toggles across many pins (such as bus-enable patterns) can momentarily collapse the GND reference if not damped. Internal 'turbo-bit' and 'slow-slew' options in the macrocell configuration can also be used to slow edge rates on non-timing-critical outputs.
合规信息
N suffix denotes Pb-free / RoHS-compliant terminal finish per Altera/Intel ordering information. Halogen-free status not explicitly stated in the manufacturer datasheet or distributor listings reviewed.