EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera
料号： EPM3128ATI144-10 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
EPM3128ATI144-10 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style logic blocks with a central interconnect matrix, providing deterministic timing and instant-on behavior. CPLDs occupy the middle ground between small logic ICs (gates, muxes, flip-flops) and larger FPGAs, making them ideal for glue-logic, bus-interface bridging, power-up sequencing, and state-machine replacement. The MAX 3000A family sits within the broader hierarchy of programmable logic devices (PLDs) -> CPLDs -> non-volatile logic devices -> digital semiconductors.
Key features of the EPM3128ATI144-10 include 128 macro cells distributed across 8 Logic Array Blocks (LABs), 96 user I/Os (note: 96 is the canonical MAX 3000A count for the 144-pin TQFP; the 98 figure cited on some aggregator pages reflects legacy Altera documentation), in-system programmability (ISP) through the IEEE 1149.1 JTAG interface, and PCI-SIG-compliant I/O drivers supporting the PCI Local Bus Specification, Revision 2.2 in the -4, -5, -6, -7, and -10 speed grades. The device operates from a 3.3-V supply with 5-V-tolerant I/O available on certain pins.
Architecturally, the device uses a uniform interconnect matrix (the Programmable Interconnect Array, or PIA) that routes signals between LABs with predictable, fixed delays, eliminating the timing-closure variability of FPGA fabrics. The EEPROM configuration memory provides true non-volatile storage, so the part powers up in a known functional state without external boot memory. Counter frequencies reach 192.3 MHz in the -7 speed grade and 98 MHz typical for the -10 grade.
Typical applications include industrial control glue logic, parallel bus interface bridging (e.g., address decoding between a microcontroller and an SRAM bank), power-sequencing controllers for multi-rail systems, peripheral expansion logic, and PCI-bus glue functions. The wide operating temperature range (-40C to +85C industrial) makes it suitable for factory automation, automotive body electronics, and outdoor telecommunications equipment.
When designing with this part, allocate the JTAG pins (TCK, TMS, TDI, TDO) carefully because they are dedicated for boundary-scan and ISP. Decouple each VCCINT/VCCIO pair with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and use a ground plane on layer 2 for return-current continuity.
This page synthesizes verified distributor pricing, drop-in alternative cross-references, and practical PCB-layout design notes for the EPM3128ATI144-10 that are not assembled in the manufacturer datasheet alone.
直接替换替代料： EPM3128ATI144-10 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM3128ATI144-10 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, RoHS Status, Usable Gates, Configuration Memory.
快速对比工具——选择替代料号进行并排对比：
EPM3128ATC144-10N
✅ 直接替换✓ 有现货
$6.56 / 个
查看数据手册 →EPM3128ATC144-10
✅ 直接替换✓ 有现货
$6.2 / 个
查看数据手册 →EPM3128ATC144-7N
✅ 直接替换✓ 有现货
$9.25 / 个
查看数据手册 →EPM3128ATC144-5N
✅ 直接替换✓ 有现货
$13.75 / 个
查看数据手册 →EPM3128ATC144-7
✅ 直接替换✓ 有现货
$8.1 / 个
查看数据手册 →EPM3128ATI144-10 最大额定值与电气特性
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 98 |
| 引脚数量 | 144 |
| 封装 | TQFP-144 (FINE LINE) |
| Supply Voltage (VCCINT) | 3.3 V |
| Pin-to-Pin Delay | 10 ns (speed grade -10) |
| Counter Frequency | 98 MHz typical |
| Logic Family | CMOS, EEPROM-based |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) |
| 工作温度 | -40C to +85C (Industrial) |
| 安装类型 | Surface Mount (Gull-Wing TQFP) |
| RoHS 状态 | Compliant (lead-free TQFP) |
EPM3128ATI144-10 引脚配置
| 引脚 1 | I/O — User I/O pin (per datasheet pin table) |
| 引脚 2 | I/O — User I/O pin |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | I/O — User I/O pin |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | I/O — User I/O pin |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | GND — Ground |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | I/O — User I/O pin |
| 引脚 16 | I/O — User I/O pin |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | I/O — User I/O pin |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | GND — Ground |
| 引脚 28 | I/O — User I/O pin |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | I/O — User I/O pin |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | GND — Ground |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | I/O — User I/O pin |
| 引脚 46 | I/O — User I/O pin |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | I/O — User I/O pin |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | GND — Ground |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | GND — Ground |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | I/O — User I/O pin |
| 引脚 78 | I/O — User I/O pin |
| 引脚 79 | I/O — User I/O pin |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | GND — Ground |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | I/O — User I/O pin |
| 引脚 86 | I/O — User I/O pin |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | I/O — User I/O pin |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | I/O — User I/O pin |
| 引脚 91 | I/O — User I/O pin |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | I/O — User I/O pin |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | GND — Ground |
| 引脚 98 | TDI — JTAG Test Data In |
| 引脚 99 | TMS — JTAG Test Mode Select |
| 引脚 100 | TCK — JTAG Test Clock |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | I/O — User I/O pin |
| 引脚 105 | I/O — User I/O pin |
| 引脚 106 | I/O — User I/O pin |
| 引脚 107 | I/O — User I/O pin |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | GND — Ground |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | I/O — User I/O pin |
| 引脚 114 | I/O — User I/O pin |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | I/O — User I/O pin |
| 引脚 120 | I/O — User I/O pin |
| 引脚 121 | I/O — User I/O pin |
| 引脚 122 | I/O — User I/O pin |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | GND — Ground |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | I/O — User I/O pin |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | I/O — User I/O pin |
| 引脚 131 | I/O — User I/O pin |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | I/O — User I/O pin |
| 引脚 135 | I/O — User I/O pin |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | GND — Ground |
| 引脚 140 | TDO — JTAG Test Data Out |
| 引脚 141 | I/O — User I/O pin |
| 引脚 142 | I/O — User I/O pin |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
典型应用
EPM3128ATI144-10 适用于 7 应用s: Industrial Control Glue Logic, PCI Bus Address Decoding, Multi-Rail Power Sequencing Controller, Microcontroller Bus Interface Bridging, Peripheral Expansion Logic (GPIO Extender), Legacy Peripheral Replacement / State Machine, Automotive Body Electronics.
Industrial Control Glue Logic
The EPM3128ATI144-10's 128 macro cells and deterministic 10 ns pin-to-pin delay make it ideal for industrial glue-logic between microcontrollers, sensors, and actuators in factory automation. The device replaces 5-10 discrete 74-series logic ICs with a single non-volatile part, freeing PCB space and reducing BOM cost. Its industrial -40C to +85C temperature range tolerates cabinet-mounted environments and -25C cold-start conditions. Use it for address decoding, I/O expansion, watchdog timing, and interrupt prioritization in PLC backplanes. The JTAG ISP allows field re-programming via the controller's existing test header, eliminating the need for socketed PROMs and reducing service downtime. Estimated: power consumption is roughly 100-150 mW at 3.3 V with all I/O toggling, so a small LDO is sufficient.
推荐
PCI Bus Address Decoding
In PCI 2.2 add-in cards the EPM3128ATI144-10 provides PCI-compliant chip-select generation and bus-cycle decoding for memory and I/O windows. The 3.3-V core with 5-V-tolerant I/O directly interfaces to PCI bus signals, and the -10 speed grade (10 ns pin-to-pin) comfortably meets the 33 MHz PCI clock period with timing margin. With 98 user I/Os the device can decode up to 4-6 address ranges plus generate the active-low FRAME, IRDY, and TRDY enable signals for downstream peripherals. The JTAG interface allows post-assembly programming of the device's EEPROM image directly on the PCI card, simplifying board bring-up. Designers should reserve the four JTAG pins (TCK/TMS/TDI/TDO) and route them to a 4-pin header for boundary-scan test access.
推荐
Multi-Rail Power Sequencing Controller
The EPM3128ATI144-10's instant-on EEPROM-based logic makes it a reliable power-sequencing controller for systems with strict rail-order requirements (e.g., FPGA core before I/O before transceivers). With 98 user I/Os the device can monitor up to 12-15 PG (power-good) inputs and assert 12-15 EN lines to downstream regulators with programmable delays implemented as on-chip counters. The 10 ns pin-to-pin delay gives sub-microsecond sequencing resolution. Industrial temperature rating ensures cold-boot reliability in outdoor and automotive systems. Use the JTAG port to reprogram sequence tables during development without replacing the part. Estimated: each rail-enable line can source/sink 25 mA; for higher current, buffer with a discrete MOSFET driver.
推荐
Microcontroller Bus Interface Bridging
The EPM3128ATI144-10 bridges mismatched buses between a 16-bit microcontroller, an SRAM bank, an LCD controller, and an external peripheral. Its 98 user I/Os handle multiple chip-selects, RD/WR strobes, and address-latch enable signals simultaneously, while the deterministic 10 ns timing matches legacy 8051, PIC, and ARM7 external-bus timing without wait-state insertion. The EEPROM configuration retains the bus map across power cycles, eliminating boot-up glitching. Industrial temperature grade supports outdoor HMI panels. Designers should place the device close to the microcontroller to minimize propagation skew and use the JTAG port to revise address maps in the field.
推荐
Peripheral Expansion Logic (GPIO Extender)
When a microcontroller runs out of GPIO pins, the EPM3128ATI144-10 adds 98 configurable I/Os with interrupt and timer functions, accessible over a 3-wire SPI or I2C-like interface from the host. Each CPLD I/O can be individually set as input, output, or open-drain with internal pull-up. The instant-on EEPROM image lets I/O defaults be safe at power-up without firmware intervention, critical for fail-safe system designs. The 10 ns propagation delay enables debounced contact-input scanning at mechanical-switch rates (>1 kHz). Industrial temperature rating suits appliance and HVAC controllers.
推荐
Legacy Peripheral Replacement / State Machine
The EPM3128ATI144-10 replaces obsolete TTL/CMOS state-machine ICs (e.g., 74LS194 shift-register chains, custom PAL/GAL sequencers) with a single reprogrammable device. A 144-pin TQFP occupies the same board area as 3-4 SOIC-16 PLD packages and offers far higher functional density. The 128 macro cells can encode multi-state FSMs, custom instruction decoders, and waveform generators. With JTAG ISP the design can be revised without depopulation, and the industrial temperature rating suits factory-floor retrofits. Engineers migrating from GAL22V10 or PALCE16V8 designs should leverage Altera's MAX+PLUS II or Quartus II legacy mode for direct import.
推荐
Automotive Body Electronics
In automotive body-control modules the EPM3128ATI144-10 handles load-driver multiplexing, bulb-out detection, and LIN/CAN bus wake-up logic. The 3.3-V core with 5-V-tolerant I/O interfaces directly to 12-V automotive battery rails via external transceivers. Industrial temperature grade (-40C to +85C) covers under-hood and cabin environments. Note: this part is NOT AEC-Q100 qualified; for safety-critical or powertrain applications use a dedicated automotive CPLD such as the MAX II automotive variant. The JTAG ISP enables end-of-line programming during vehicle assembly.
推荐
推荐产品汇总
工程参考数据： EPM3128ATI144-10 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM3128ATC144-10N | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATC144-5N | EPM3128ATC144-7 |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | TQFP-144 (FINE LINE) | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same |
| Family | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| Speed Grade | -10 (10 ns pin-to-pin) | -10 (10 ns) | -10 (10 ns) | -7 (~7 ns, faster) | -5 (~5 ns, fastest) | -7 (~7 ns, faster) |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Counter Frequency | 98 MHz typical | 98 MHz | 98 MHz | 192.3 MHz (higher) | 227.3 MHz (highest) | 192.3 MHz (higher) |
| User I/Os | 98 | 98 | 98 | 98 | 98 | 98 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
关键差异点
- Industrial temperature range (-40C to +85C) （对比 EPM3128ATC144-10N)
- Standard -10 speed grade with 98 MHz counter frequency （对比 XC9572XL-10TQG144I (Xilinx))
- PCI 2.2 compliant I/O buffers in -10 speed grade （对比 EPM240T100C5N (MAX II))
设计说明
The EPM3128ATI144-10 requires a clean 3.3-V VCCINT rail. Place a 10 uF bulk tantalum or ceramic capacitor near the package and at least six 0.1 uF ceramic decoupling capacitors distributed around the VCCINT/VCCIO pin pairs (per the MAX 3000A reference design). Estimated: Icore is approximately 30 mA quiescent, rising to 80-120 mA with high-frequency logic activity. A low-noise LDO such as the TPS7A4533 or LM1117-3.3 is recommended for noise-sensitive analog-adjacent designs. Do not power the device from a switching converter without adequate output filtering, as supply ripple couples directly into I/O thresholds.
For the 144-pin TQFP (FINE LINE), use a 4-layer PCB with a continuous ground plane on layer 2 beneath the device. Route JTAG signals (TCK, TMS, TDI, TDO) on the top layer directly to a 4-pin or 10-pin JTAG header with no stubs. Maintain 50-ohm characteristic impedance on TCK if it exceeds 50 mm. Keep high-speed I/O traces short (<50 mm) and use a ground guard via fence on either side of clock and output-enable traces to reduce crosstalk. The exposed thermal pad (if present on this TQFP variant) should be soldered to a 5x5 mm copper pour connected to GND.
Do not confuse the EPM3128ATI144-10 (industrial temperature, -40C to +85C) with the EPM3128ATC144-10 (commercial 0C to +70C) - the part marking 'I' vs 'C' after 'TI144' is the only visual differentiator on the top marking. Both share the same JTAG IDCODE, so a Quartus II programmer will program either one; verify your inventory and BOM carefully. Do not exceed the 3.6-V absolute-maximum VCCINT rating - the device does NOT have 5-V tolerance on VCCINT, only on selected I/O pins per the datasheet. Finally, ensure the JTAG chain is correctly ordered when multiple devices share the bus; the EPM3128ATI144-10 expects TCK rising-edge sampling and TDI/TDO order per IEEE 1149.1.
合规信息
RoHS compliant per lead-free TQFP-144 package. Not AEC-Q100 qualified; not recommended for automotive safety-critical applications without additional qualification. Halogen-free status not explicitly stated in available data - marked unknown.
