EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
料号： EPM3128ATI144-10N ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $16.13 | $16.13 |
| 10 | $14.52 | $145.20 |
| 100 | $12.9 | $1,290.00 |
| 500 | $11.61 | $5,805.00 |
| 1,000 | $10.32 | $10,320.00 |
EPM3128ATI144-10N 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the hierarchy between discrete logic gates (PAL/GAL) and higher-density FPGAs. Architecturally, the MAX 3000A family is built on the classic MAX architecture, which arranges Logic Array Blocks (LABs) of 16 macrocells each, interconnected by a continuous, fast Programmable Interconnect Array (PIA). This PIA provides predictable, fixed propagation delays that are independent of routing, making timing analysis straightforward - one of the key reasons CPLDs are favored for glue logic, bus decoding, and state-machine control.
Key features of the EPM3128ATI144-10N include 128 macrocells (2.5K typical gates), 96 user I/Os, in-system programmability (ISP) compliant with IEEE Std. 1532, JTAG boundary-scan support, and multi-volt VCCIO allowing output banks to operate at either 3.3 V or 2.5 V for mixed-voltage interfacing. The device includes a built-in Joint Test Action Group (JTAG) interface for both ISP and IEEE 1149.1 boundary-scan test. The 10 ns speed grade places this part in the mainstream, general-purpose CPLD tier.
Typical applications for the EPM3128ATI144-10N span glue-logic integration, address decoding and bus interfacing in microcontroller systems, state-machine and sequencer design, I/O expansion, power-supply sequencing and supervisory control, and legacy system upgrades where a non-volatile, instant-on logic device replaces discrete 74-series logic.
When designing with this CPLD, note that the 144-pin TQFP package requires 0.5 mm pitch PCB layout. Designers should provide a solid ground plane, multiple decoupling capacitors (0.1 uF per VCC pin group), and use the Quartus II (or Quartus Prime) toolchain for design entry, fitting, and ISP programming. Industrial temperature grade is supported.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single source for sourcing and substitution decisions.
直接替换替代料： EPM3128ATI144-10N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM3128ATI144-10N （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, Configuration Memory, Propagation Delay (tPD), Programming Interface.
快速对比工具——选择替代料号进行并排对比：
EPM3128ATC144-10N
✅ 直接替换✓ 有现货
$6.56 / 个
查看数据手册 →EPM3128ATC144-10
✅ 直接替换✓ 有现货
$6.2 / 个
查看数据手册 →EPM3128ATC144-7N
✅ 直接替换✓ 有现货
$9.25 / 个
查看数据手册 →EPM3128ATI144-10AA
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EPM3128ATI144-10
✅ 直接替换✓ 有现货
$10.85 / 个
查看数据手册 →EPM7128AETC144-10N
✅ 直接替换✓ 有现货
$22.56 / 个
查看数据手册 →EPM3128ATI144-10N 最大额定值与电气特性
| Family | MAX 3000A |
| Logic Type | CMOS EEPROM-based CPLD |
| Macrocells | 128 |
| Typical Gates | 2.5K |
| User I/Os | 96 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Internal Frequency | 98 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| Output Bank Voltage (VCCIO) | 3.3 V or 2.5 V |
| 封装 | 144-pin TQFP |
| 安装类型 | Surface Mount |
| 工作温度 | Industrial -40C to +85C |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) |
| Configuration Memory | Non-volatile EEPROM |
| RoHS 状态 | Compliant |
EPM3128ATI144-10N 引脚配置
| 引脚 1 | I/O — User I/O (bank 1) |
| 引脚 2 | I/O — User I/O (bank 1) |
| 引脚 3 | I/O — User I/O (bank 1) |
| 引脚 4 | I/O — User I/O (bank 1) |
| 引脚 5 | I/O — User I/O (bank 1) |
| 引脚 6 | I/O — User I/O (bank 1) |
| 引脚 7 | I/O — User I/O (bank 1) |
| 引脚 8 | I/O — User I/O (bank 1) |
| 引脚 9 | VCCINT — 3.3 V core supply |
| 引脚 10 | I/O — User I/O (bank 1) |
| 引脚 11 | I/O — User I/O (bank 1) |
| 引脚 12 | I/O — User I/O (bank 1) |
| 引脚 13 | GND — Ground |
| 引脚 14 | I/O — User I/O (bank 1) |
| 引脚 15 | I/O — User I/O (bank 1) |
| 引脚 16 | I/O — User I/O (bank 1) |
| 引脚 17 | I/O — User I/O (bank 1) |
| 引脚 18 | I/O — User I/O (bank 1) |
| 引脚 19 | I/O — User I/O (bank 1) |
| 引脚 20 | I/O — User I/O (bank 1) |
| 引脚 21 | GND — Ground |
| 引脚 22 | I/O — User I/O (bank 2) |
| 引脚 23 | I/O — User I/O (bank 2) |
| 引脚 24 | I/O — User I/O (bank 2) |
| 引脚 25 | I/O — User I/O (bank 2) |
| 引脚 26 | I/O — User I/O (bank 2) |
| 引脚 27 | I/O — User I/O (bank 2) |
| 引脚 28 | I/O — User I/O (bank 2) |
| 引脚 29 | I/O — User I/O (bank 2) |
| 引脚 30 | VCCIO1 — I/O bank 1 supply (3.3 V or 2.5 V) |
| 引脚 31 | I/O — User I/O (bank 2) |
| 引脚 32 | I/O — User I/O (bank 2) |
| 引脚 33 | I/O — User I/O (bank 2) |
| 引脚 34 | GND — Ground |
| 引脚 35 | I/O — User I/O (bank 2) |
| 引脚 36 | I/O — User I/O (bank 2) |
| 引脚 37 | I/O — User I/O (bank 2) |
| 引脚 38 | I/O — User I/O (bank 2) |
| 引脚 39 | I/O — User I/O (bank 2) |
| 引脚 40 | I/O — User I/O (bank 2) |
| 引脚 41 | GND — Ground |
| 引脚 42 | I/O — User I/O (bank 2) |
| 引脚 43 | I/O — User I/O (bank 2) |
| 引脚 44 | I/O — User I/O (bank 2) |
| 引脚 45 | I/O — User I/O (bank 2) |
| 引脚 46 | I/O — User I/O (bank 2) |
| 引脚 47 | I/O — User I/O (bank 2) |
| 引脚 48 | I/O — User I/O (bank 2) |
| 引脚 49 | I/O — User I/O (bank 2) |
| 引脚 50 | VCCINT — 3.3 V core supply |
| 引脚 51 | I/O — User I/O (bank 2) |
| 引脚 52 | I/O — User I/O (bank 2) |
| 引脚 53 | I/O — User I/O (bank 2) |
| 引脚 54 | GND — Ground |
| 引脚 55 | I/O — User I/O (bank 2) |
| 引脚 56 | I/O — User I/O (bank 2) |
| 引脚 57 | I/O — User I/O (bank 2) |
| 引脚 58 | I/O — User I/O (bank 2) |
| 引脚 59 | I/O — User I/O (bank 2) |
| 引脚 60 | I/O — User I/O (bank 2) |
| 引脚 61 | GND — Ground |
| 引脚 62 | TDI — JTAG test data in (IEEE 1149.1) |
| 引脚 63 | TMS — JTAG test mode select |
| 引脚 64 | TCK — JTAG test clock |
| 引脚 65 | NC — Not connected (per datasheet) |
| 引脚 66 | VCCIO2 — I/O bank 2 supply (3.3 V or 2.5 V) |
| 引脚 67 | TDO — JTAG test data out |
| 引脚 68 | I/O — User I/O (bank 3) |
| 引脚 69 | I/O — User I/O (bank 3) |
| 引脚 70 | I/O — User I/O (bank 3) |
| 引脚 71 | I/O — User I/O (bank 3) |
| 引脚 72 | I/O — User I/O (bank 3) |
| 引脚 73 | GND — Ground |
| 引脚 74 | I/O — User I/O (bank 3) |
| 引脚 75 | I/O — User I/O (bank 3) |
| 引脚 76 | I/O — User I/O (bank 3) |
| 引脚 77 | I/O — User I/O (bank 3) |
| 引脚 78 | I/O — User I/O (bank 3) |
| 引脚 79 | I/O — User I/O (bank 3) |
| 引脚 80 | I/O — User I/O (bank 3) |
| 引脚 81 | VCCINT — 3.3 V core supply |
| 引脚 82 | I/O — User I/O (bank 3) |
| 引脚 83 | I/O — User I/O (bank 3) |
| 引脚 84 | I/O — User I/O (bank 3) |
| 引脚 85 | GND — Ground |
| 引脚 86 | I/O — User I/O (bank 3) |
| 引脚 87 | I/O — User I/O (bank 3) |
| 引脚 88 | I/O — User I/O (bank 3) |
| 引脚 89 | I/O — User I/O (bank 3) |
| 引脚 90 | I/O — User I/O (bank 3) |
| 引脚 91 | I/O — User I/O (bank 3) |
| 引脚 92 | GND — Ground |
| 引脚 93 | I/O — User I/O (bank 3) |
| 引脚 94 | I/O — User I/O (bank 3) |
| 引脚 95 | I/O — User I/O (bank 3) |
| 引脚 96 | I/O — User I/O (bank 3) |
| 引脚 97 | I/O — User I/O (bank 3) |
| 引脚 98 | I/O — User I/O (bank 3) |
| 引脚 99 | I/O — User I/O (bank 3) |
| 引脚 100 | I/O — User I/O (bank 3) |
| 引脚 101 | VCCINT — 3.3 V core supply |
| 引脚 102 | I/O — User I/O (bank 4) |
| 引脚 103 | I/O — User I/O (bank 4) |
| 引脚 104 | I/O — User I/O (bank 4) |
| 引脚 105 | I/O — User I/O (bank 4) |
| 引脚 106 | I/O — User I/O (bank 4) |
| 引脚 107 | I/O — User I/O (bank 4) |
| 引脚 108 | I/O — User I/O (bank 4) |
| 引脚 109 | I/O — User I/O (bank 4) |
| 引脚 110 | VCCIO3 — I/O bank 3 supply (3.3 V or 2.5 V) |
| 引脚 111 | I/O — User I/O (bank 4) |
| 引脚 112 | I/O — User I/O (bank 4) |
| 引脚 113 | I/O — User I/O (bank 4) |
| 引脚 114 | GND — Ground |
| 引脚 115 | I/O — User I/O (bank 4) |
| 引脚 116 | I/O — User I/O (bank 4) |
| 引脚 117 | I/O — User I/O (bank 4) |
| 引脚 118 | I/O — User I/O (bank 4) |
| 引脚 119 | I/O — User I/O (bank 4) |
| 引脚 120 | I/O — User I/O (bank 4) |
| 引脚 121 | GND — Ground |
| 引脚 122 | I/O — User I/O (bank 4) |
| 引脚 123 | I/O — User I/O (bank 4) |
| 引脚 124 | I/O — User I/O (bank 4) |
| 引脚 125 | I/O — User I/O (bank 4) |
| 引脚 126 | I/O — User I/O (bank 4) |
| 引脚 127 | I/O — User I/O (bank 4) |
| 引脚 128 | I/O — User I/O (bank 4) |
| 引脚 129 | I/O — User I/O (bank 4) |
| 引脚 130 | VCCINT — 3.3 V core supply |
| 引脚 131 | I/O — User I/O (bank 4) |
| 引脚 132 | I/O — User I/O (bank 4) |
| 引脚 133 | I/O — User I/O (bank 4) |
| 引脚 134 | GND — Ground |
| 引脚 135 | OE2 — Output enable 2 / global control |
| 引脚 136 | OE1 — Output enable 1 / global control |
| 引脚 137 | GND — Ground |
| 引脚 138 | CLK2 — Global clock input 2 |
| 引脚 139 | CLK1 — Global clock input 1 |
| 引脚 140 | VCCIO4 — I/O bank 4 supply (3.3 V or 2.5 V) |
| 引脚 141 | INPUT/GCLK1 — Input / global clear |
| 引脚 142 | MSEL1 — Mode select 1 (ISP configuration) |
| 引脚 143 | MSEL0 — Mode select 0 (ISP configuration) |
| 引脚 144 | CONF_DONE — Configuration done (open-drain) |
典型应用
EPM3128ATI144-10N 适用于 6 应用s: Microcontroller Bus Glue Logic, Power-Supply Sequencing & Supervisory Control, Address Decoding & Chip-Select Generation, I/O Expansion & Level Translation, Industrial State Machines & Sequencers, Legacy Logic Replacement (74-Series Substitution).
Microcontroller Bus Glue Logic
The EPM3128ATI144-10N's 128 macrocells and 96 user I/Os make it ideal for microcontroller bus glue logic where address decoding, chip-select generation, and wait-state insertion must be implemented in deterministic, non-volatile hardware. Placed between an MCU and peripheral memories or ASICs, the CPLD replaces dozens of 74-series logic packages with a single device. The 10 ns tPD adds less than one 50 MHz bus cycle of latency, which is invisible to most MCU reads. Instant-on EEPROM configuration eliminates the boot-PROM overhead typical of SRAM-based FPGAs.
推荐
Power-Supply Sequencing & Supervisory Control
The EPM3128ATI144-10N is well suited to multi-rail power-supply sequencing controllers in industrial and communications equipment. Its 96 I/Os can drive PG (power-good) and EN lines for many voltage rails, while state-machine logic implemented in macrocells enforces turn-on and turn-off ordering. The non-volatile EEPROM configuration means sequencing starts correctly on every power cycle without boot latency. 3.3 V VCCINT and selectable 3.3 V / 2.5 V VCCIO allow direct interface to most modern point-of-load regulators.
推荐
Address Decoding & Chip-Select Generation
The MAX 3000A's wide AND-OR product-term macrocells excel at address decoding, where many input pins (often 16-24 address bits) must be combined to generate a single chip-select output. The EPM3128ATI144-10N's 96 user I/Os comfortably accept a 24-bit address bus plus several qualifier lines (read/write, chip-enable, burst) and produce up to 96 chip-select outputs - more than enough for full memory and I/O decoding on embedded processor platforms. The 10 ns tPD keeps decode latency below one clock cycle at typical 33-50 MHz bus speeds.
推荐
I/O Expansion & Level Translation
With selectable 3.3 V / 2.5 V VCCIO banks, the EPM3128ATI144-10N is a natural voltage-level translator between mixed-voltage domains on a single board. It can be configured to translate parallel buses between a 3.3 V FPGA and 2.5 V memory or peripheral ASICs without dedicated level-shifter ICs. The 96 user I/Os support wide data buses and the macrocell registers double as small FIFO / handshake buffers when both clock domains are crossed in the same device.
推荐
Industrial State Machines & Sequencers
The industrial -40C to +85C operating temperature range of the EPM3128ATI144-10N makes it suitable for factory-floor controllers, motor-control sequencers, and other industrial applications. The 128 macrocells can host multiple parallel Moore or Mealy state machines for stepper-motor commutation, conveyor indexing, or safety-interlock logic. Non-volatile EEPROM configuration means the controller resumes its state machine exactly where it left off after power cycles - critical for unattended industrial equipment.
推荐
Legacy Logic Replacement (74-Series Substitution)
A single EPM3128ATI144-10N can replace an entire board of 74HC/74AHC glue logic - address latches, bus transceivers, parity generators, interrupt controllers, and shift registers. This consolidation reduces PCB area, improves reliability by eliminating inter-chip wiring, and adds reconfigurability for late design changes. The IEEE Std. 1532-compliant ISP allows the replacement device to be re-programmed on the production line without removing it from the board, accelerating ECO cycles and reducing inventory of legacy logic SKUs.
推荐
推荐产品汇总
工程参考数据： EPM3128ATI144-10N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM3128ATC144-10N | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATI144-10AA | EPM3128ATI144-10 | EPM7128AETC144-10N |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 7000AE |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 96 | 96 | 96 | 96 | 96 | 96 | 100 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7 ns (-30%, faster) | 10 ns | 10 ns | 10 ns |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Lead-Free Finish | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | No (legacy) | Yes (Pb-free) |
关键差异点
- Industrial temperature grade vs commercial-temperature same-die variant （对比 EPM3128ATC144-10N)
- Pb-free RoHS-compliant lead finish （对比 EPM3128ATI144-10 (no -N suffix))
- 10 ns tPD provides 30% timing margin over legacy 74HC logic （对比 Discrete 74HC / 74AHC glue logic)
- Same TQFP-144 footprint, faster speed-grade upgrade available （对比 EPM3128ATC144-7N)
设计说明
The 144-pin TQFP package has 0.5 mm lead pitch, which demands a 4-layer PCB with a continuous ground plane under the device to control impedance and crosstalk on the 96 user I/Os. Place a 0.1 uF X7R decoupling capacitor within 5 mm of every VCCINT pin and every VCCIO bank pin, plus a single 10 uF bulk tantalum or ceramic capacitor per VCCIO bank. Avoid routing signal traces beneath the package body or the exposed die-pad region. The recommended land pattern and thermal land are shown in the MAX 3000A device handbook.
Although the MAX 3000A family uses a non-volatile EEPROM configuration with predictable, fixed routing delays, the 96 high-frequency I/Os at 98 MHz can still generate simultaneous-switching noise (SSN). Reserve one GND pin adjacent to each switching output bank and add a ferrite bead on the VCCIO supply if the bank drives long traces (>50 mm) or >8 simultaneous outputs. JTAG signals TCK and TMS should be guarded with ground traces on both sides for noise immunity.
Do not mix VCCIO bank voltages beyond the supported 3.3 V or 2.5 V options - 1.8 V peripherals require an external level shifter. The CONF_DONE pin is open-drain and requires an external 10 kohm pull-up to VCCIO. Setting OE1/OE2 incorrectly will tristate entire I/O banks and masquerade as a 'dead' board. When using ISP through the JTAG pins, ensure that TMS and TDI are not held low at power-up to prevent unintended entry into JTAG states.
The MAX 3000A family has very low static power consumption (typical Icc < 50 mA at 3.3 V) because the EEPROM configuration has no DC refresh current. However, dynamic power scales with toggle frequency and output loading. At 96 I/Os toggling at 98 MHz into 30 pF loads each, total dynamic power can reach ~500 mW. Provide a copper pour area of at least 1 square inch on the top layer connected to the exposed thermal pad (TQFP variant) to keep junction temperature below 125 C at industrial ambient.
合规信息
Pb-free matte-tin lead finish per JEDEC J-STD-609. Industrial temperature grade -40C to +85C. Not AEC-Q100 qualified (industrial, not automotive).