EPM3128ATI144-7N vs EPM3128ATC144-7N 对比

详细并排对比 EPM3128ATI144-7N 出自 Altera 和 EPM3128ATC144-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3128ATI144-7N EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A

EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A

EPM3128ATI144-7N ⚠ 最后一次采购

规格对比

参数 EPM3128ATI144-7N EPM3128ATC144-7N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 有效
库存状态 有库存 有库存
单价(USD) $9.95 $9.25
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Capacity 2.5K gates —
Macrocells 128 —
Maximum Frequency (fMAX) 129.9 MHz —
Pin-to-Pin Propagation Delay 7.5 ns (speed grade -7) —
User I/O Pins 96 —
Core Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 3.3 V / 2.5 V / 1.8 V 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Programmable Logic Technology CMOS EEPROM —
Programming Interface JTAG (IEEE Std 1149.1) in-system programmable —
封装 144-pin TQFP TQFP-144 (20 x 20 mm, 0.5 mm pitch)
Terminal Pitch 0.5 mm —
JEDEC Package Code S-PQFP-G144 —
工作温度 -40C to +85C (industrial) 0 °C to +70 °C (commercial)
MultiVolt I/O Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic) —
Series — MAX 3000A
Architecture — EEPROM-based, MAX architecture
Number of Macrocells — 128
Number of Usable Gates — Up to 10,000
User I/Os — 96
引脚数量 — 144
Logic Family — CMOS
Propagation Delay (tPD) — 7.5 ns (pin-to-pin, -7 speed grade)
Counter Frequency — Up to 227.3 MHz
In-System Programmability (ISP) — Yes, via JTAG (IEEE 1149.1)
PCI Compliance — Compatible with PCI Local Bus Specification Rev. 2.2
安装类型 — Surface Mount (SMD/SMT)
RoHS 状态 — Lead-free (-7N suffix indicates Pb-free finish)

数据手册与资源

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